Issued Patents All Time
Showing 101–125 of 265 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7334320 | Method of making an electronic fuse with improved ESD tolerance | — | 2008-02-26 |
| 7309898 | Method and apparatus for providing noise suppression in an integrated circuit | Raminderpal Singh | 2007-12-18 |
| 7303968 | Semiconductor device and method having multiple subcollectors formed on a common wafer | James S. Dunn, Louis D. Lanzerotti | 2007-12-04 |
| 7282771 | Structure and method for latchup suppression | — | 2007-10-16 |
| 7242071 | Semiconductor structure | Xuefeng Liu, Robert M. Rassel | 2007-07-10 |
| 7202136 | Silicon germanium heterojunction bipolar transistor with carbon incorporation | Louis D. Lanzerotti, Brian P. Ronan | 2007-04-10 |
| 7200825 | Methodology of quantification of transmission probability for minority carrier collection in a semiconductor chip | Anne E. Watson | 2007-04-03 |
| 7173310 | Lateral lubistor structure and method | Jack A. Mandelman | 2007-02-06 |
| 7166904 | Structure and method for local resistor element in integrated circuit technology | Jason P. Gill, Terence B. Hook, Randy W. Mann, William J. Murphy, William R. Tonti | 2007-01-23 |
| 7138701 | Electrostatic discharge protection networks for triple well semiconductor devices | James P. Pequignot, Jeffrey H. Sloan, Douglas W. Stout | 2006-11-21 |
| 7138669 | Silicon germanium heterojunction bipolar transistor with carbon incorporation | Louis D. Lanzerotti, Brian P. Ronan | 2006-11-21 |
| 7136268 | Tunable ESD trigger and power clamp circuit | Andreas D. Stricker | 2006-11-14 |
| 7134099 | ESD design, verification and checking system and method of use | David S. Collins, Donald L. Jordan, Sue Ellen Strang | 2006-11-07 |
| 7129545 | Charge modulation network for multiple power domains for silicon-on-insulator technology | David Cain, Jeffrey P. Gambino, Norman J. Rohrer, Daryl M. Seitzer | 2006-10-31 |
| 7119401 | Tunable semiconductor diodes | — | 2006-10-10 |
| 7109584 | Dendrite growth control circuit | Douglas B. Hershberger, Michael J. Zierak | 2006-09-19 |
| 7106164 | Apparatus and method for electronic fuse with improved ESD tolerance | — | 2006-09-12 |
| 7102867 | Method, apparatus and circuit for latchup suppression in a gate-array ASIC environment | — | 2006-09-05 |
| 7089520 | Methodology for placement based on circuit function and latchup sensitivity | — | 2006-08-08 |
| 7067914 | Dual chip stack method for electro-static discharge protection of integrated circuits | John C. Malinowski, Edmund J. Sprogis | 2006-06-27 |
| 7064416 | Semiconductor device and method having multiple subcollectors formed on a common wafer | James S. Dunn, Louis D. Lanzerotti | 2006-06-20 |
| 7041581 | Method and structure for improving latch-up immunity using non-dopant implants | Louis D. Lanzerotu | 2006-05-09 |
| 7020857 | Method and apparatus for providing noise suppression in a integrated circuit | Raminderpal Singh | 2006-03-28 |
| 6996786 | Latch-up analysis and parameter modification | — | 2006-02-07 |
| 6975015 | Modulated trigger device | Michael J. Zierak | 2005-12-13 |