Issued Patents All Time
Showing 151–175 of 265 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6574078 | Method and apparatus for providing electrostatic discharge protection of a magnetic head using a mechanical switch and an electrostatic discharge device network | — | 2003-06-03 |
| 6563176 | Asymmetrical semiconductor device for ESD protection | Robert J. Gauthier, Jr. | 2003-05-13 |
| 6552879 | Variable voltage threshold ESD protection | — | 2003-04-22 |
| 6552406 | SiGe transistor, varactor and p-i-n velocity saturated ballasting element for BiCMOS peripheral circuits and ESD networks | — | 2003-04-22 |
| 6549061 | Electrostatic discharge power clamp circuit | Alan B. Botula, David Hui | 2003-04-15 |
| 6548338 | Integrated high-performance decoupling capacitor and heat sink | Kerry Bernstein, Robert M. Geffken, Wilbur D. Pricer, Anthony K. Stamper | 2003-04-15 |
| 6531741 | Dual buried oxide film SOI structure and method of manufacturing the same | Michael Hargrove | 2003-03-11 |
| 6526548 | Method for evaluating circuit design for ESD electrostatic discharge robustness | — | 2003-02-25 |
| 6512296 | Semiconductor structure having heterogenous silicide regions having titanium and molybdenum | Robert J. Gauthier, Jr., Randy W. Mann | 2003-01-28 |
| 6498385 | Post-fuse blow corrosion prevention structure for copper fuses | Timothy H. Daubenspeck, Daniel C. Edelstein, Robert M. Geffken, William T. Motsiff, Anthony K. Stamper | 2002-12-24 |
| 6476445 | Method and structures for dual depth oxygen layers in silicon-on-insulator processes | Jeffrey S. Brown, Andres Bryant, Robert J. Gauthier, Jr., Randy W. Mann | 2002-11-05 |
| 6465870 | ESD robust silicon germanium transistor with emitter NP-block mask extrinsic base ballasting resistor with doped facet region | — | 2002-10-15 |
| 6455919 | Internally ballasted silicon germanium transistor | Ciaran J. Brennan | 2002-09-24 |
| 6455902 | BiCMOS ESD circuit with subcollector/trench-isolated body mosfet for mixed signal analog/digital RF applications | — | 2002-09-24 |
| 6441462 | Self-aligned SiGe NPN with improved ESD robustness using wide emitter polysilicon extension | Louis D. Lanzerotti | 2002-08-27 |
| 6441410 | MOSFET with lateral resistor ballasting | Robert J. Gauthier, Jr., Randy W. Mann | 2002-08-27 |
| 6433985 | ESD network with capacitor blocking element | Richard Q. Williams | 2002-08-13 |
| 6433609 | Double-gate low power SOI active clamp network for single power supply and multiple power supply applications | — | 2002-08-13 |
| 6432809 | Method for improved passive thermal flow in silicon on insulator devices | William R. Tonti | 2002-08-13 |
| 6429489 | Electrostatic discharge power clamp circuit | Alan B. Botula, David Hui | 2002-08-06 |
| 6429482 | Halo-free non-rectifying contact on chip with halo source/drain diffusion | James A. Culp, Jawahar P. Nayak, Werner Rausch, Melanie J. Sherony, Noah Zamdmer | 2002-08-06 |
| 6429066 | Method for producing a polysilicon circuit element | Jeffrey S. Brown, Robert J. Gauthier, Jr. | 2002-08-06 |
| 6429045 | Structure and process for multi-chip chip attach with reduced risk of electrostatic discharge damage | Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak, H. Bernhard Pogge +1 more | 2002-08-06 |
| 6426244 | Process of forming a thick oxide field effect transistor | Michael Hargrove, Mario M. Pelella | 2002-07-30 |
| 6420766 | Transistor having raised source and drain | Jeffrey S. Brown, James S. Dunn, Steven J. Holmes, David V. Horak, Robert K. Leidy | 2002-07-16 |