Issued Patents All Time
Showing 201–225 of 265 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6232639 | Method and structure to reduce latch-up using edge implants | Faye D. Baker, Jeffrey S. Brown, Robert J. Gauthier, Jr., Steven J. Holmes, Robert K. Leidy +1 more | 2001-05-15 |
| 6232163 | Method of forming a semiconductor diode with depleted polysilicon gate structure | Robert J. Gauthier, Jr., Jeffrey S. Brown | 2001-05-15 |
| 6229372 | Active clamp network for multiple voltages | Benjamin W. Mashak, Robert R. Williams, David Hui | 2001-05-08 |
| 6218704 | ESD protection structure and method | Jeffrey S. Brown, Steven J. Holmes, Robert K. Leidy | 2001-04-17 |
| 6198136 | Support chips for buffer circuits | James M. Never | 2001-03-06 |
| 6187617 | Semiconductor structure having heterogeneous silicide regions and method for forming same | Robert J. Gauthier, Jr., Randy W. Mann | 2001-02-13 |
| 6171918 | Depleted poly mosfet structure and method | Jeffrey S. Brown, Robert J. Gauthier, Jr., Edward J. Nowak, Minh H. Tong | 2001-01-09 |
| 6166420 | Method and structure of high and low K buried oxide for SoI technology | Robert J. Gauthier, Jr., Dominic J. Schepis | 2000-12-26 |
| 6157530 | Method and apparatus for providing ESD protection | James P. Pequignot, Tariq Rahman, Jeffrey H. Sloan, Douglas W. Stout | 2000-12-05 |
| 6144086 | Structure for improved latch-up using dual depth STI with impurity implant | Jeffrey S. Brown, Robert J. Gauthier, Jr., Randy W. Mann | 2000-11-07 |
| 6136656 | Method to create a depleted poly MOSFET | Jeffrey S. Brown, Robert J. Gauthier, Jr., William R. Tonti | 2000-10-24 |
| 6118155 | Integrated ESD structures for use in ESD circuitry | — | 2000-09-12 |
| 6100013 | Method for forming transistors with raised source and drains and device formed thereby | Jeffery Brown, James S. Dunn, Steven J. Holmes, David V. Horak, Robert K. Leidy | 2000-08-08 |
| 6100143 | Method of making a depleted poly-silicon edged MOSFET structure | Jeffrey S. Brown, Robert J. Gauthier, Jr. | 2000-08-08 |
| 6097068 | Semiconductor device fabrication method and apparatus using connecting implants | Jeffrey S. Brown, Stephen Furkay, Robert J. Gauthier, Jr., Xiaowei Tian, Minh H. Tong | 2000-08-01 |
| 6097069 | Method and structure for increasing the threshold voltage of a corner device | Jeffrey S. Brown, Robert J. Gauthier, Jr. | 2000-08-01 |
| 6096584 | Silicon-on-insulator and CMOS-on-SOI double film fabrication process with a coplanar silicon and isolation layer and adding a second silicon layer on one region | John J. Ellis-Monaghan | 2000-08-01 |
| 6086627 | Method of automated ESD protection level verification | Roy Bass, Daniel J. Nickel, Daniel Canty Sullivan | 2000-07-11 |
| 6081409 | TiC MR-head magnetic shield dummy shield spark gap | Timothy Scott Hughbanks, Neil Leslie Robertson, Albert John Wallash | 2000-06-27 |
| 6074899 | 3-D CMOS-on-SOI ESD structure and method | — | 2000-06-13 |
| 6075399 | Switchable active clamp network | David Hui | 2000-06-13 |
| 6071803 | Electrical contact to buried SOI structures | Matthew J. Rutten | 2000-06-06 |
| 6057184 | Semiconductor device fabrication method using connecting implants | Jeffrey S. Brown, Stephen Furkay, Robert J. Gauthier, Jr., Xiaowei Tian, Minh H. Tong | 2000-05-02 |
| 6049445 | Overvoltage and electrostatic discharge protection for a receiver circuit | Robert J. Gauthier, Jr. | 2000-04-11 |
| 6034397 | Silicon-on-insulator body- and dual gate-coupled diode for electrostatic discharge (ESD) applications | — | 2000-03-07 |