Issued Patents All Time
Showing 226–250 of 265 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6034388 | Depleted polysilicon circuit element and method for producing the same | Jeffrey S. Brown, Robert J. Gauthier, Jr. | 2000-03-07 |
| 6033949 | Method and structure to reduce latch-up using edge implants | Faye D. Baker, Jeffrey S. Brown, Robert J. Gauthier, Jr., Steven J. Holmes, Robert K. Leidy +1 more | 2000-03-07 |
| 6015993 | Semiconductor diode with depleted polysilicon gate structure and method | Robert J. Gauthier, Jr., Jeffrey S. Brown | 2000-01-18 |
| 5998848 | Depleted poly-silicon edged MOSFET structure and method | Jeffrey S. Brown, Robert J. Gauthier, Jr. | 1999-12-07 |
| 5952695 | Silicon-on-insulator and CMOS-on-SOI double film structures | John J. Ellis-Monaghan | 1999-09-14 |
| 5945713 | Electrostatic discharge protection circuits for mixed voltage interface and multi-rail disconnected power grid applications | — | 1999-08-31 |
| 5943254 | Multichip semiconductor structures with consolidated circuitry and programmable ESD protection for input/output nodes | Paul E. Bakeman, Jr., Claude L. Bertin, Erik L. Hedberg, James M. Leas | 1999-08-24 |
| 5939767 | Structure and process for buried diode formation in CMOS | Jeffrey S. Brown, Steven J. Holmes, Robert K. Leidy | 1999-08-17 |
| 5930098 | Multichip semiconductor structures with interchip electrostatic discharge protection, and fabrication methods therefore | Paul E. Bakeman, Jr. | 1999-07-27 |
| 5923067 | 3-D CMOS-on-SOI ESD structure and method | — | 1999-07-13 |
| 5894230 | Modified keeper half-latch receiver circuit | — | 1999-04-13 |
| 5889293 | Electrical contact to buried SOI structures | Matthew J. Rutten | 1999-03-30 |
| 5882967 | Process for buried diode formation in CMOS | Jeffrey S. Brown, Steven J. Holmes, Robert K. Leidy | 1999-03-16 |
| 5872378 | Dual thin oxide ESD network for nonvolatile memory applications | Russell E. Rose, Robert C. Szafranski | 1999-02-16 |
| 5867888 | Magnetic head/silicon chip integration method | Albert John Wallash | 1999-02-09 |
| 5861330 | Method and structure to reduce latch-up using edge implants | Faye D. Baker, Jeffrey S. Brown, Robert J. Gauthier, Jr., Steven J. Holmes, Robert K. Leidy +1 more | 1999-01-19 |
| 5811857 | Silicon-on-insulator body-coupled gated diode for electrostatic discharge (ESD) and analog applications | Fariborz Assaderaghi, Louis L. Hsu, Jack A. Mandelman, Ghavam G. Shahidi | 1998-09-22 |
| 5807791 | Methods for fabricating multichip semiconductor structures with consolidated circuitry and programmable ESD protection for input/output nodes | Claude L. Bertin, Erik L. Hedberg, James M. Leas | 1998-09-15 |
| 5789964 | Decoupling capacitor network for off-state operation | — | 1998-08-04 |
| 5786237 | Method for forming a monolithic electronic module by stacking planar arrays of integrated circuit chips | Martha Ashley Clark Cockerill, John Maltabes, Loretta J. O'Connor | 1998-07-28 |
| 5777829 | Method and apparatus for providing electrostatic discharge protection for an inductive coil of a magnetic transducer | Albert John Wallash | 1998-07-07 |
| 5771571 | Method for manufacturing thin film slider with on-board multi-layer integrated circuit | Albert John Wallash | 1998-06-30 |
| 5761009 | Having parastic shield for electrostatic discharge protection | Timothy Scott Hughbanks, Neil Leslie Robertson, Albert John Wallash | 1998-06-02 |
| 5731945 | Multichip semiconductor structures with consolidated circuitry and programmable ESD protection for input/output nodes | Claude L. Bertin, Erik L. Hedberg, James M. Leas | 1998-03-24 |
| 5731941 | Electrostatic discharge suppression circuit employing trench capacitor | Michael Hargrove | 1998-03-24 |