Issued Patents All Time
Showing 26–50 of 115 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9570354 | Asymmetric high-K dielectric for reducing gate induced drain leakage | Anthony I. Chou, Arvind Kumar, Chung-Hsun Lin, Claude Ortolland, Jonathan T. Shaw | 2017-02-14 |
| 9559010 | Asymmetric high-k dielectric for reducing gate induced drain leakage | Anthony I. Chou, Arvind Kumar, Chung-Hsun Lin, Claude Ortolland, Jonathan T. Shaw | 2017-01-31 |
| 9543213 | Asymmetric high-k dielectric for reducing gate induced drain leakage | Anthony I. Chou, Arvind Kumar, Chung-Hsun Lin, Claude Ortolland, Jonathan T. Shaw | 2017-01-10 |
| 9443929 | Shallow trench isolation structure having a nitride plug | Byeong Y. Kim | 2016-09-13 |
| 9437496 | Merged source drain epitaxy | Michael P. Chudzik, Brian J. Greene, Edward P. Maciejewski, Kevin McStay, Chengwen Pei +1 more | 2016-09-06 |
| 9425079 | Semiconductor structure with integrated passive structures | Anthony I. Chou, Arvind Kumar, Renee T. Mo | 2016-08-23 |
| 9412667 | Asymmetric high-k dielectric for reducing gate induced drain leakage | Anthony I. Chou, Arvind Kumar, Chung-Hsun Lin, Claude Ortolland, Jonathan T. Shaw | 2016-08-09 |
| 9401325 | Planar polysilicon regions for precision resistors and electrical fuses and method of fabrication | Anthony I. Chou, Arvind Kumar, Renee T. Mo | 2016-07-26 |
| 9287399 | Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels | Bhupesh Chandra, Paul Chang, Gregory G. Freeman, Dechao Guo, Judson R. Holt +6 more | 2016-03-15 |
| 9269786 | Silicon nitride layer deposited at low temperature to prevent gate dielectric regrowth high-K metal gate field effect transistors | Anthony I. Chou, Arvind Kumar, Claude Ortolland, Kai Zhao | 2016-02-23 |
| 9252146 | Work function adjustment by carbon implant in semiconductor devices including gate structure | Yue Liang, Dechao Guo, William K. Henson, Yanfeng Wang | 2016-02-02 |
| 9240482 | Asymmetric stressor DRAM | Ravi K. Dasaka, Ahmed Nayaz Noemaun, Karen A. Nummy, Katsunori Onishi, Paul C. Parries +3 more | 2016-01-19 |
| 9219059 | Semiconductor structure with integrated passive structures | Anthony I. Chou, Arvind Kumar, Renee T. Mo | 2015-12-22 |
| 9184301 | Planar and nanowire field effect transistors | Sarunya Bangsaruntip, Guy M. Cohen, Jeffrey W. Sleight | 2015-11-10 |
| 9136321 | Low energy ion implantation of a junction butting region | Katsunori Onishi, Paul C. Parries, Chengwen Pei, Geng Wang | 2015-09-15 |
| 9105718 | Butted SOI junction isolation structures and devices and method of fabrication | Jeffrey B. Johnson, Hasan M. Nayfeh, Viorel Ontalus, Robert R. Robison | 2015-08-11 |
| 9082877 | Complementary metal oxide semiconductor (CMOS) device having gate structures connected by a metal gate conductor | Yue Liang, Dureseti Chidambarrao, Brian J. Greene, William K. Henson, Unoh Kwon +1 more | 2015-07-14 |
| 9064972 | Method of forming a gated diode structure for eliminating RIE damage from cap removal | Anthony I. Chou, Arvind Kumar, Edward P. Maciejewski, Dustin K. Slisher | 2015-06-23 |
| 9040399 | Threshold voltage adjustment for thin body MOSFETs | MaryJane Brodsky, Ming Cai, Dechao Guo, William K. Henson, Yue Liang +3 more | 2015-05-26 |
| 8952460 | Germanium oxide free atomic layer deposition of silicon oxide and high-k gate dielectric on germanium containing channel for CMOS devices | MaryJane Brodsky, Murshed Chowdhury, Michael P. Chudzik, Min Dai, Siddarth A. Krishnan +1 more | 2015-02-10 |
| 8940595 | Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels | Bhupesh Chandra, Paul Chang, Gregory G. Freeman, Dechao Guo, Judson R. Holt +6 more | 2015-01-27 |
| 8916950 | Shallow trench isolation structure having a nitride plug | Byeong Y. Kim | 2014-12-23 |
| 8835231 | Methods of forming contacts for nanowire field effect transistors | Sarunya Bangsaruntip, Guy M. Cohen, Jeffrey W. Sleight | 2014-09-16 |
| 8836048 | Field effect transistor device having a hybrid metal gate stack | Cyril Cabral, Jr., Josephine B. Chang, Michael P. Chudzik, Martin M. Frank, Michael A. Guillorn +2 more | 2014-09-16 |
| 8829616 | Method and structure for body contacted FET with reduced body resistance and source to drain contact leakage | Anthony I. Chou, Murshed Chowdhury, Arvind Kumar | 2014-09-09 |