Issued Patents All Time
Showing 101–125 of 262 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10622489 | Vertical tunnel FET with self-aligned heterojunction | Chun Wing Yeung, Choonghyun Lee, Ruqiang Bao | 2020-04-14 |
| 10622379 | Structure and method to form defect free high-mobility semiconductor fins on insulator | Veeraraghavan S. Basker, Oleg Gluschenkov, Alexander Reznicek | 2020-04-14 |
| 10615083 | Formation of common interfacial layer on Si/SiGe dual channel complementary metal oxide semiconductor device | Ruqiang Bao, Hemanth Jagannathan, Choonghyun Lee | 2020-04-07 |
| 10600885 | Vertical fin field effect transistor devices with self-aligned source and drain junctions | Kangguo Cheng, Juntao Li, Choonghyun Lee | 2020-03-24 |
| 10600695 | Channel strain formation in vertical transport FETS with dummy stressor materials | Choonghyun Lee, Kangguo Cheng, Juntao Li | 2020-03-24 |
| 10600694 | Gate metal patterning for tight pitch applications | Alexander Reznicek, Joshua M. Rubin, Junli Wang | 2020-03-24 |
| 10593797 | Vertical transport field effect transistor structure with self-aligned top junction through early top source/drain epitaxy | Brent A. Anderson, Hemanth Jagannathan, Junli Wang | 2020-03-17 |
| 10586769 | Contact formation in semiconductor devices | Oleg Gluschenkov, Jiseok Kim, Zuoguang Liu, Hiroaki Niimi | 2020-03-10 |
| 10573746 | VTFET devices utilizing low temperature selective epitaxy | Hemanth Jagannathan | 2020-02-25 |
| 10573727 | Vertical transistor device | Brent A. Anderson, Huiming Bu, Fee Li Lie, Junli Wang | 2020-02-25 |
| 10573567 | Sacrificial cap for forming semiconductor contact | Praneet Adusumilli, Zuoguang Liu, Jie Yang, Chun Wing Yeung | 2020-02-25 |
| 10573521 | Gate metal patterning to avoid gate stack attack due to excessive wet etching | Junli Wang, Alexander Reznicek, Joshua M. Rubin | 2020-02-25 |
| 10559566 | Reduction of multi-threshold voltage patterning damage in nanosheet device structure | Choonghyun Lee, Kangguo Cheng, Juntao Li | 2020-02-11 |
| 10553716 | Formation of a bottom source-drain for vertical field-effect transistors | Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Junli Wang | 2020-02-04 |
| 10541331 | Fabrication of a vertical fin field effect transistor with an asymmetric gate structure | Junli Wang | 2020-01-21 |
| 10535773 | FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formation | Dechao Guo, Hemanth Jagannathan, Gen Tsutsui, Chun-Chen Yeh | 2020-01-14 |
| 10529851 | Forming bottom source and drain extension on vertical transport FET (VTFET) | Kangguo Cheng, Juntao Li, Choonghyun Lee | 2020-01-07 |
| 10529828 | Method of forming vertical transistor having dual bottom spacers | Oleg Gluschenkov, Sanjay C. Mehta, Alexander Reznicek | 2020-01-07 |
| 10510617 | CMOS VFET contacts with trench solid and liquid phase epitaxy | Oleg Gluschenkov, Zuoguang Liu, Hiroaki Niimi, Tenko Yamashita | 2019-12-17 |
| 10504997 | Silicon-germanium Fin structure having silicon-rich outer surface | Hemanth Jagannathan, Choonghyun Lee, Koji Watanabe | 2019-12-10 |
| 10490667 | Three-dimensional field effect device | Huimei Zhou, Su Chen Fan, Peng Xu, Nicolas Loubet | 2019-11-26 |
| 10475923 | Method and structure for forming vertical transistors with various gate lengths | Kangguo Cheng, Choonghyun Lee, Juntao Li | 2019-11-12 |
| 10461154 | Bottom isolation for nanosheet transistors on bulk substrate | Yi Song, Chi-Chun Liu, Zhenxing Bi | 2019-10-29 |
| 10453940 | Vertical field effect transistor with strained channel region extension | Choonghyun Lee, Juntao Li, Kangguo Cheng | 2019-10-22 |
| 10453824 | Structure and method to form nanosheet devices with bottom isolation | Chun Wing Yeung | 2019-10-22 |