Issued Patents All Time
Showing 76–100 of 262 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10777464 | Low thermal budget top source and drain region formation for vertical transistors | Alexander Reznicek, Oleg Gluschenkov | 2020-09-15 |
| 10763343 | Effective junction formation in vertical transistor structures by engineered bottom source/drain epitaxy | Alexander Reznicek | 2020-09-01 |
| 10756175 | Inner spacer formation and contact resistance reduction in nanosheet transistors | Choonghyun Lee, Kangguo Cheng, Juntao Li | 2020-08-25 |
| 10756170 | VFET devices with improved performance | Kangguo Cheng, Juntao Li, Choonghyun Lee | 2020-08-25 |
| 10755985 | Gate metal patterning for tight pitch applications | Alexander Reznicek, Joshua M. Rubin, Junli Wang | 2020-08-25 |
| 10749012 | Formation of self-aligned bottom spacer for vertical transistors | Ruqiang Bao, Hemanth Jagannathan, Choonghyun Lee | 2020-08-18 |
| 10734518 | Substantially defect free relaxed heterogeneous semiconductor fins on bulk substrates | Veeraraghavan S. Basker, Oleg Gluschenkov, Alexander Reznicek | 2020-08-04 |
| 10734490 | Bipolar junction transistor (BJT) with 3D wrap around emitter | Choonghyun Lee, Injo Ok, Soon-Cheon Seo | 2020-08-04 |
| 10734281 | Method and structure to fabricate a nanoporous membrane | Zhenxing Bi, Kangguo Cheng, Hao Tang | 2020-08-04 |
| 10714399 | Gate-last process for vertical transport field-effect transistor | Choonghyun Lee, Hemanth Jagannathan | 2020-07-14 |
| 10707329 | Vertical fin field effect transistor device with reduced gate variation and reduced capacitance | Juntao Li, Kangguo Cheng, Choonghyun Lee | 2020-07-07 |
| 10700062 | Vertical transport field-effect transistors with uniform threshold voltage | Choonghyun Lee, Kangguo Cheng, Juntao Li | 2020-06-30 |
| 10692868 | Contact formation through low-temperature epitaxial deposition in semiconductor devices | Oleg Gluschenkov, Hiroaki Niimi, Tenko Yamashita, Chun-Chen Yeh | 2020-06-23 |
| 10686057 | Vertical transport FET devices having a sacrificial doped layer | Choonghyun Lee, Kangguo Cheng, Juntao Li | 2020-06-16 |
| 10680102 | Reduction of top source/drain external resistance and parasitic capacitance in vertical transistors | Choonghyun Lee, Kangguo Cheng, Juntao Li | 2020-06-09 |
| 10679901 | Differing device characteristics on a single wafer by selective etch | Huimei Zhou, Gen Tsutsui, Ruqiang Bao | 2020-06-09 |
| 10665714 | Vertical transistors with various gate lengths | Juntao Li, Kangguo Cheng, Choonghyun Lee | 2020-05-26 |
| 10665698 | Reducing gate-induced-drain-leakage current in a transistor by forming an enhanced band gap layer at the channel-to-drain interface | Choonghyun Lee, Kangguo Cheng, Juntao Li | 2020-05-26 |
| 10651308 | Self aligned top extension formation for vertical transistors | Oleg Gluschenkov, Sanjay C. Mehta, Alexander Reznicek | 2020-05-12 |
| 10651295 | Forming a fin using double trench epitaxy | Veeraraghavan S. Basker, Pouya Hashemi, Alexander Reznicek | 2020-05-12 |
| 10651089 | Low thermal budget top source and drain region formation for vertical transistors | Alexander Reznicek, Oleg Gluschenkov | 2020-05-12 |
| 10644138 | Fin field-effect transistors with enhanced strain and reduced parasitic capacitance | Kangguo Cheng, Juntao Li, Choonghyun Lee | 2020-05-05 |
| 10643894 | Surface area and Schottky barrier height engineering for contact trench epitaxy | Jody A. Fronheiser, Hiroaki Niimi, Balasubramanian Pranatharthiharan, Mark V. Raymond, Tenko Yamashita | 2020-05-05 |
| 10643893 | Surface area and Schottky barrier height engineering for contact trench epitaxy | Jody A. Fronheiser, Hiroaki Niimi, Balasubramanian Pranatharthiharan, Mark V. Raymond, Tenko Yamashita | 2020-05-05 |
| 10628404 | Vertical transistor and method of forming the vertical transistor | Fee Li Lie, Junli Wang | 2020-04-21 |