SM

Shogo Mochizuki

IBM: 244 patents #112 of 70,183Top 1%
Globalfoundries: 15 patents #235 of 4,424Top 6%
RE Renesas Electronics: 14 patents #183 of 4,529Top 5%
ET Elpis Technologies: 3 patents #8 of 121Top 7%
SS Stmicroelectronics Sa: 1 patents #938 of 1,676Top 60%
GU Globalfoundries U.S.: 1 patents #344 of 665Top 55%
NC Nippon Light Metal Company: 1 patents #203 of 499Top 45%
Nsk: 1 patents #937 of 1,559Top 65%
📍 Mechanicville, NY: #1 of 102 inventorsTop 1%
🗺 New York: #83 of 115,490 inventorsTop 1%
Overall (All Time): #1,757 of 4,157,543Top 1%
262
Patents All Time

Issued Patents All Time

Showing 126–150 of 262 patents

Patent #TitleCo-InventorsDate
10439063 Close proximity and lateral resistance reduction for bottom source/drain epitaxy in vertical transistor devices Alexander Reznicek, Jingyun Zhang, Xin Miao 2019-10-08
10439049 Nanosheet device with close source drain proximity Veeraraghavan S. Basker, Alexander Reznicek 2019-10-08
10439043 Formation of self-aligned bottom spacer for vertical transistors Ruqiang Bao, Hemanth Jagannathan, Choonghyun Lee 2019-10-08
10431503 Sacrificial cap for forming semiconductor contact Praneet Adusumilli, Zuoguang Liu, Jie Yang, Chun Wing Yeung 2019-10-01
10431502 Maskless epitaxial growth of phosphorus-doped Si and boron-doped SiGe (Ge) for advanced source/drain contact Choonghyun Lee, Chun Wing Yeung, Hemanth Jagannathan 2019-10-01
10418288 Techniques for forming different gate length vertical transistors with dual gate oxide Ruqiang Bao, Choonghyun Lee, Chun Wing Yeung 2019-09-17
10411120 Self-aligned inner-spacer replacement process using implantation Robin Hsin Kuo Chao, Michael A. Guillorn, Chi-Chun Liu, Chun Wing Yeung 2019-09-10
10388766 Vertical transport FET (VFET) with dual top spacer Michael P. Belyansky, Choonghyun Lee 2019-08-20
10381479 Interface charge reduction for SiGe surface Devendra K. Sadana, Dechao Guo, Joel P. de Souza, Ruqiang Bao, Stephen W. Bedell +3 more 2019-08-13
10381442 Low resistance source drain contact formation Oleg Gluschenkov, Zuoguang Liu, Hiroaki Niimi, Chun-Chen Yeh 2019-08-13
10361306 High acceptor level doping in silicon germanium Mona A. Ebrish, Oleg Gluschenkov, Alexander Reznicek 2019-07-23
10347581 Contact formation in semiconductor devices Oleg Gluschenkov, Jiseok Kim, Zuoguang Liu, Hiroaki Niimi 2019-07-09
10340363 Fabrication of vertical field effect transistors with self-aligned bottom insulating spacers Choonghyun Lee 2019-07-02
10333000 Forming strained channel with germanium condensation Kangguo Cheng, Jie Yang 2019-06-25
10325815 Vertical transport fin field effect transistors having different channel lengths Ruqiang Bao, Choonghyun Lee, Chun Wing Yeung 2019-06-18
10326017 Formation of a bottom source-drain for vertical field-effect transistors Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Junli Wang 2019-06-18
10319643 Vertical FET with strained channel Choonghyun Lee, Kangguo Cheng, Juntao Li 2019-06-11
10319836 Effective junction formation in vertical transistor structures by engineered bottom source/drain epitaxy Alexander Reznicek 2019-06-11
10312349 Reducing resistance of bottom source/drain in vertical channel devices Junli Wang 2019-06-04
10312377 Localized fin width scaling using a hydrogen anneal Veeraraghavan S. Basker, Tenko Yamashita, Chun-Chen Yeh 2019-06-04
10297507 Self-aligned vertical field-effect transistor with epitaxially grown bottom and top source drain regions Kangguo Cheng, Tenko Yamashita, Chen Zhang 2019-05-21
10297614 Gate top spacer for FinFET Veeraraghavan S. Basker, Oleg Gluschenkov, Alexander Reznicek 2019-05-21
10290747 MIS capacitor for finned semiconductor structure Keith E. Fogel, Pouya Hashemi, Alexander Reznicek 2019-05-14
10283636 Vertical FET with strained channel Junli Wang 2019-05-07
10276687 Formation of self-aligned bottom spacer for vertical transistors Ruqiang Bao, Hemanth Jagannathan, Choonghyun Lee 2019-04-30