Issued Patents All Time
Showing 176–200 of 262 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10068920 | Silicon germanium fins on insulator formed by lateral recrystallization | Alexander Reznicek, Veeraraghavan S. Basker, Nicolas L. Breil, Oleg Gluschenkov | 2018-09-04 |
| 10056484 | VTFET devices utilizing low temperature selective epitaxy | Hemanth Jagannathan | 2018-08-21 |
| 10056503 | MIS capacitor for finned semiconductor structure | Keith E. Fogel, Pouya Hashemi, Alexander Reznicek | 2018-08-21 |
| 10032912 | Semiconductor integrated structure having an epitaxial SiGe layer extending from silicon-containing regions formed between segments of oxide regions | Pierre Morin, Kangguo Cheng, Jody A. Fronheiser, Xiuyu Cai, Juntao Li +3 more | 2018-07-24 |
| 10020303 | Methods for forming FinFETs having epitaxial Si S/D extensions with flat top surfaces on a SiGe seed layer | Hong He, Chiahsun Tseng, Chun-Chen Yeh, Yunpeng Yin | 2018-07-10 |
| 10020384 | Forming a fin using double trench epitaxy | Veeraraghavan S. Basker, Pouya Hashemi, Alexander Reznicek | 2018-07-10 |
| 10008417 | Vertical transport fin field effect transistors having different channel lengths | Ruqiang Bao, Choonghyun Lee, Chun Wing Yeung | 2018-06-26 |
| 9997407 | Voidless contact metal structures | Veeraraghavan S. Basker, Nicolas L. Breil, Oleg Gluschenkov, Alexander Reznicek | 2018-06-12 |
| 9991382 | Vertical field effect transistor with abrupt extensions at a bottom source/drain structure | Alexander Reznicek | 2018-06-05 |
| 9991258 | FinFETs with non-merged epitaxial S/D extensions having a SiGe seed layer on insulator | Hong He, Chiahsun Tseng, Chun-Chen Yeh, Yunpeng Yin | 2018-06-05 |
| 9991255 | FinFETs with non-merged epitaxial S/D extensions on a seed layer and having flat top surfaces | Hong He, Chiahsun Tseng, Chun-Chen Yeh, Yunpeng Yin | 2018-06-05 |
| 9985114 | Fin field effect transistor structure and method to form defect free merged source and drain epitaxy for low external resistance | Veeraraghavan S. Basker, Oleg Gluschenkov, Alexander Reznicek | 2018-05-29 |
| 9972682 | Low resistance source drain contact formation | Oleg Gluschenkov, Zuoguang Liu, Hiroaki Niimi, Chun-Chen Yeh | 2018-05-15 |
| 9966253 | Forming nanotips | Kangguo Cheng, Ramachandra Divakaruni, Juntao Li | 2018-05-08 |
| 9960272 | Bottom contact resistance reduction on VFET | Ruqiang Bao, Choonghyun Lee, Hemanth Jagannathan | 2018-05-01 |
| 9954102 | Vertical field effect transistor with abrupt extensions at a bottom source/drain structure | Alexander Reznicek | 2018-04-24 |
| 9954058 | Self-aligned air gap spacer for nanosheet CMOS devices | Alexander Reznicek, Joshua M. Rubin, Junli Wang | 2018-04-24 |
| 9954103 | Bottom spacer formation for vertical transistor | Oleg Gluschenkov, Sanjay C. Mehta, Alexander Reznicek | 2018-04-24 |
| 9947748 | Dielectric isolated SiGe fin on bulk substrate | Huiming Bu, Tenko Yamashita | 2018-04-17 |
| 9947532 | Forming zig-zag trench structure to prevent aspect ratio trapping defect escape | Judson R. Holt, Alexander Reznicek, Melissa A. Smith | 2018-04-17 |
| 9947689 | Semiconductor device structure with 110-PFET and 111-NFET current flow direction | Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2018-04-17 |
| 9941391 | Method of forming vertical transistor having dual bottom spacers | Oleg Gluschenkov, Sanjay C. Mehta, Alexander Reznicek | 2018-04-10 |
| 9941175 | Dielectric isolated SiGe fin on bulk substrate | Huiming Bu, Tenko Yamashita | 2018-04-10 |
| 9941302 | Structure and method to form defect free high-mobility semiconductor fins on insulator | Veeraraghavan S. Basker, Oleg Gluschenkov, Alexander Reznicek | 2018-04-10 |
| 9923084 | Forming a fin using double trench epitaxy | Veeraraghavan S. Basker, Pouya Hashemi, Alexander Reznicek | 2018-03-20 |