Issued Patents All Time
Showing 151–175 of 262 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10276695 | Self-aligned inner-spacer replacement process using implantation | Robin Hsin Kuo Chao, Michael A. Guillorn, Chi-Chun Liu, Chun Wing Yeung | 2019-04-30 |
| 10269652 | Vertical transistor top epitaxy source/drain and contact structure | Oleg Gluschenkov, Sanjay C. Mehta, Alexander Reznicek | 2019-04-23 |
| 10262904 | Vertical transistor top epitaxy source/drain and contact structure | Oleg Gluschenkov, Sanjay C. Mehta, Alexander Reznicek | 2019-04-16 |
| 10256159 | Formation of common interfacial layer on Si/SiGe dual channel complementary metal oxide semiconductor device | Ruqiang Bao, Hemanth Jagannathan, Choonghyun Lee | 2019-04-09 |
| 10256327 | Forming a fin using double trench epitaxy | Veeraraghavan S. Basker, Pouya Hashemi, Alexander Reznicek | 2019-04-09 |
| 10249714 | Method of forming epitaxial buffer layer for finFET source and drain junction leakage reduction | Dechao Guo, Andreas Scholze, Chun-Chen Yeh | 2019-04-02 |
| 10249502 | Low resistance source drain contact formation with trench metastable alloys and laser annealing | Oleg Gluschenkov, Zuoguang Liu, Hiroaki Niimi, Tenko Yamashita, Chun-Chen Yeh | 2019-04-02 |
| 10249758 | FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formation | Dechao Guo, Hemanth Jagannathan, Gen Tsutsui, Chun-Chen Yeh | 2019-04-02 |
| 10242919 | Vertical transport fin field effect transistors having different channel lengths | Ruqiang Bao, Choonghyun Lee, Chun Wing Yeung | 2019-03-26 |
| 10243043 | Self-aligned air gap spacer for nanosheet CMOS devices | Alexander Reznicek, Joshua M. Rubin, Junli Wang | 2019-03-26 |
| 10236360 | Method of forming vertical transistor having dual bottom spacers | Oleg Gluschenkov, Sanjay C. Mehta, Alexander Reznicek | 2019-03-19 |
| 10229975 | Fabrication of silicon-germanium fin structure having silicon-rich outer surface | Hemanth Jagannathan, Choonghyun Lee, Koji Watanabe | 2019-03-12 |
| 10217863 | Fabrication of a vertical fin field effect transistor with an asymmetric gate structure | Junli Wang | 2019-02-26 |
| 10177169 | Semiconductor device structure with 110-PFET and 111-NFET current flow direction | Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2019-01-08 |
| 10170620 | Substantially defect free relaxed heterogeneous semiconductor fins on bulk substrates | Veeraraghavan S. Basker, Oleg Gluschenkov, Alexander Reznicek | 2019-01-01 |
| 10164103 | Forming strained channel with germanium condensation | Kangguo Cheng, Jie Yang | 2018-12-25 |
| 10141426 | Vertical transistor device | Brent A. Anderson, Huiming Bu, Fee Li Lie, Junli Wang | 2018-11-27 |
| 10134763 | Gate top spacer for finFET | Veeraraghavan S. Basker, Oleg Gluschenkov, Alexander Reznicek | 2018-11-20 |
| 10128372 | Bottom contact resistance reduction on VFET | Ruqiang Bao, Choonghyun Lee, Hemanth Jagannathan | 2018-11-13 |
| 10115824 | Forming a contact for a semiconductor device | Oleg Gluschenkov, Zuoguang Liu, Hiroaki Niimi, Ruilong Xie | 2018-10-30 |
| 10103065 | Gate metal patterning for tight pitch applications | Alexander Reznicek, Joshua M. Rubin, Junli Wang | 2018-10-16 |
| 10096713 | FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formation | Dechao Guo, Hemanth Jagannathan, Gen Tsutsui, Chun-Chen Yeh | 2018-10-09 |
| 10084082 | Bottom contact resistance reduction on VFET | Ruqiang Bao, Choonghyun Lee, Hemanth Jagannathan | 2018-09-25 |
| 10084065 | Reducing resistance of bottom source/drain in vertical channel devices | Junli Wang | 2018-09-25 |
| 10079299 | Self aligned top extension formation for vertical transistors | Oleg Gluschenkov, Sanjay C. Mehta, Alexander Reznicek | 2018-09-18 |