Issued Patents All Time
Showing 26–50 of 187 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8600202 | Process for enhanced 3D integration and structures generated using the same | Evan G. Colgan | 2013-12-03 |
| 8569874 | High memory density, high input/output bandwidth logic-memory structure and architecture | Evan G. Colgan, Monty M. Denneau, Klmberley A. Kelly, Roy R. Yu | 2013-10-29 |
| 8563396 | 3D integration method using SOI substrates and structures produced thereby | Roy R. Yu | 2013-10-22 |
| 8525144 | Programmable via devices | Kuan-Neng Chen | 2013-09-03 |
| 8519540 | Self-aligned dual damascene BEOL structures with patternable low- K material and methods of forming same | Shyng-Tsong Chen, Qinghuang Lin, Terry A. Spooner, Shawn Walsh | 2013-08-27 |
| 8512849 | Corrugated interfaces for multilayered interconnects | Lawrence A. Clevenger, Timothy J. Dalton, Elbert E. Huang, Carl Radens | 2013-08-20 |
| 8492869 | 3D integrated circuit device having lower-cost active circuitry layers stacked before higher-cost active circuitry layer | Mukta G. Farooq, Robert Hannon, Subramanian S. Iyer, Steven J. Koester, Fei Liu +2 more | 2013-07-23 |
| 8492239 | Homogeneous porous low dielectric constant materials | Robert L. Bruce, Geraud Jean-Michel Dubois, Theo J. Frot, Teddie Peregrino Magbitang, David L. Rath +1 more | 2013-07-23 |
| 8491987 | Selectively coated self-aligned mask | Matthew E. Colburn, Stephen M. Gates, Jeffrey Hedrick, Elbert E. Huang, Satyanarayana V. Nitta +1 more | 2013-07-23 |
| 8481423 | Methods to mitigate plasma damage in organosilicate dielectrics | John C. Arnold, Griselda Bonilla, William J. Cote, Geraud Jean-Michel Dubois, Daniel C. Edelstein +8 more | 2013-07-09 |
| 8476753 | Process for enhanced 3D integration and structures generated using the same | Evan G. Colgan, Roy R. Yu | 2013-07-02 |
| 8470706 | Methods to mitigate plasma damage in organosilicate dielectrics | John C. Arnold, Griselda Bonilla, William J. Cote, Geraud Jean-Michel Dubois, Daniel C. Edelstein +8 more | 2013-06-25 |
| 8415248 | Self-aligned dual damascene BEOL structures with patternable low-k material and methods of forming same | Shyng-Tsong Chen, Qinghuang Lin, Terry A. Spooner, Shawn Walsh | 2013-04-09 |
| 8399336 | Method for fabricating a 3D integrated circuit device having lower-cost active circuitry layers stacked before higher-cost active circuitry layer | Mukta G. Farooq, Robert Hannon, Subramanian S. Iyer, Steven J. Koester, Fei Liu +2 more | 2013-03-19 |
| 8389967 | Programmable via devices | Kuan-Neng Chen | 2013-03-05 |
| 8358011 | Interconnect structures with engineered dielectrics with nanocolumnar porosity | Matthew E. Colburn, Satya V. Nitta, Charles T. Black, Kathryn Guarini | 2013-01-22 |
| 8343868 | Device and methodology for reducing effective dielectric constant in semiconductor devices | Daniel C. Edelstein, Matthew E. Colburn, Edward C. Cooney, III, Timothy J. Dalton, John A. Fitzsimmons +10 more | 2013-01-01 |
| 8338952 | Interconnect structures with ternary patterned features generated from two lithographic processes | Matthew E. Colburn, Elbert E. Huang, Satyanarayana V. Nitta | 2012-12-25 |
| 8330262 | Processes for enhanced 3D integration and structures generated using the same | Evan G. Colgan, Roy R. Yu | 2012-12-11 |
| 8314005 | Homogeneous porous low dielectric constant materials | Geraud Jean-Michel Dubois, Teddie Peregrino Magbitang, Willi Volksen, Theo J. Frot | 2012-11-20 |
| 8298914 | 3D integrated circuit device fabrication using interface wafer as permanent carrier | Mukta G. Farooq, Robert Hannon, Subramanian S. Iyer, Steven J. Koester, Fei Liu +2 more | 2012-10-30 |
| 8243507 | Programmable via devices in back end of line level | Kuan-Neng Chen, Lia Krusin-Elbaum, Dennis M. Newns | 2012-08-14 |
| 8241995 | Bonding of substrates including metal-dielectric patterns with metal raised above dielectric | Kuan-Neng Chen, Bruce K. Furman, David L. Rath, Anna W. Topol, Cornelia K. Tsang | 2012-08-14 |
| 8129843 | Methods to mitigate plasma damage in organosilicate dielectrics using a protective sidewall spacer | John C. Arnold, Muthumanickam Sankarapandian, Hosadurga Shobha, Terry A. Spooner | 2012-03-06 |
| 8129286 | Reducing effective dielectric constant in semiconductor devices | Daniel C. Edelstein, Matthew E. Colburn, Edward C. Cooney, III, Timothy J. Dalton, John A. Fitzsimmons +10 more | 2012-03-06 |