Issued Patents All Time
Showing 751–775 of 1,139 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10163900 | Integration of vertical field-effect transistors and saddle fin-type field effect transistors | Min Gyu Sung, Kwan-Yong Lim | 2018-12-25 |
| 10157798 | Uniform bottom spacers in vertical field effect transistors | Cheng Chi, Min Gyu Sung, Tenko Yamashita | 2018-12-18 |
| 10157796 | Forming of marking trenches in structure for multiple patterning lithography | Laertis Economikos, Chanro Park, Pei Liu | 2018-12-18 |
| 10157827 | Semiconductor contact | Cheng Chi | 2018-12-18 |
| 10158003 | Epitaxial and silicide layer formation at top and bottom surfaces of semiconductor fins | Kangguo Cheng, Zuoguang Liu, Tenko Yamashita | 2018-12-18 |
| 10158021 | Vertical pillar-type field effect transistor and method | Kangguo Cheng, Tenko Yamashita | 2018-12-18 |
| 10153371 | Semiconductor device with fins including sidewall recesses | Xiuyu Cai, Qing Liu | 2018-12-11 |
| 10134903 | Vertical slit transistor with optimized AC performance | Qing Liu, Xiuyu Cai, Chun-Chen Yeh | 2018-11-20 |
| 10134840 | Series resistance reduction in vertically stacked silicon nanowire transistors | Chun-Chen Yeh, Xiuyu Cai, Qing Liu | 2018-11-20 |
| 10134633 | Self-aligned contact with CMP stop layer | Vimal Kamineni, Stan Tsai | 2018-11-20 |
| 10128334 | Field effect transistor having an air-gap gate sidewall spacer and method | Emilie Bourjot | 2018-11-13 |
| 10121702 | Methods, apparatus and system for forming source/drain contacts using early trench silicide cut | Chanro Park, Min Gyu Sung, Puneet Harischandra Suvarna | 2018-11-06 |
| 10115824 | Forming a contact for a semiconductor device | Oleg Gluschenkov, Zuoguang Liu, Shogo Mochizuki, Hiroaki Niimi | 2018-10-30 |
| 10109722 | Etch-resistant spacer formation on gate structure | Zhenxing Bi, Pietro Montanini, Eric R. Miller, Balasubramanian Pranatharthiharan, Oleg Gluschenkov +2 more | 2018-10-23 |
| 10109533 | Nanosheet devices with CMOS epitaxy and method of forming | Cheng Chi, Pietro Montanini, Tenko Yamashita, Nicolas Loubet | 2018-10-23 |
| 10103238 | Nanosheet field-effect transistor with full dielectric isolation | Hui Zang, Tek Po Rinus Lee, Haigou Huang, Min Gyu Sung, Chanro Park | 2018-10-16 |
| 10103247 | Vertical transistor having buried contact, and contacts using work function metals and silicides | Hui Zang, Kangguo Cheng, Tenko Yamashita, Chun-Chen Yeh | 2018-10-16 |
| 10096674 | Stacked nanowire device width adjustment by gas cluster ion beam (GCIB) | Kangguo Cheng, Xin Miao, Tenko Yamashita | 2018-10-09 |
| 10096692 | Vertical field effect transistor with reduced parasitic capacitance | Kangguo Cheng, Tenko Yamashita, Chun-Chen Yeh | 2018-10-09 |
| 10090202 | Source and drain epitaxial semiconductor material integration for high voltage semiconductor devices | Balasubramanian Pranatharthiharan, Junli Wang | 2018-10-02 |
| 10090193 | Integrated circuit structure incorporating a stacked pair of field effect transistors and a buried interconnect and method | Daniel Chanemougame, Lars Liebmann | 2018-10-02 |
| 10090402 | Methods of forming field effect transistors (FETS) with gate cut isolation regions between replacement metal gates | Chanro Park, Chang Ho Maeng, Pei Liu, Junsic Hong, Laertis Economikos | 2018-10-02 |
| 10084053 | Gate cuts after metal gate formation | Chanro Park, Min Gyu Sung | 2018-09-25 |
| 10083861 | HDP fill with reduced void formation and spacer damage | Huiming Bu, Andrew M. Greene, Balasubramanian Pranatharthiharan | 2018-09-25 |
| 10084068 | Self-aligned finFET formation | Cheng Chi, Fee Li Lie, Chi-Chun Liu | 2018-09-25 |