Issued Patents All Time
Showing 101–125 of 146 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9240406 | Precision trench capacitor | Kai D. Feng, Dan Moy, Chengwen Pei, Pinping Sun, Richard A. Wachnik +1 more | 2016-01-19 |
| 9196528 | Use of contacts to create differential stresses on devices | John J. Ellis-Monaghan, Jeffrey P. Gambino, Kirk D. Peterson, Jed H. Rankin | 2015-11-24 |
| 9190418 | Junction butting in SOI transistor with embedded source/drain | Anthony I. Chou, Murshed Chowdhury, Arvind Kumar | 2015-11-17 |
| 9165944 | Semiconductor device including SOI butted junction to reduce short-channel penalty | Viorel Ontalus, Xin-Yong WANG | 2015-10-20 |
| 9105707 | ZRAM heterochannel memory | Andres Bryant, Lyndon R. Logan, Edward J. Nowak | 2015-08-11 |
| 9105718 | Butted SOI junction isolation structures and devices and method of fabrication | Jeffrey B. Johnson, Shreesh Narasimha, Hasan M. Nayfeh, Viorel Ontalus | 2015-08-11 |
| 9059190 | Measuring current and resistance using combined diodes/resistor structure to monitor integrated circuit manufacturing process variations | Lyndon R. Logan, Edward J. Nowak, Jonathan K. Winslow, II | 2015-06-16 |
| 9059203 | Semiconductor-on-insulator (SOI) structure with selectivity placed sub-insulator layer void(s) and method of forming the SOI structure | Toshiharu Furukawa, Richard Q. Williams | 2015-06-16 |
| 9018024 | Creating extremely thin semiconductor-on-insulator (ETSOI) having substantially uniform thickness | Nathaniel Berliner, Kangguo Cheng, Jason E. Cummings, Toshiharu Furukawa, Jed H. Rankin +1 more | 2015-04-28 |
| 8993428 | Structure and method to create a damascene local interconnect during metal gate deposition | John J. Ellis-Monaghan, Jeffrey P. Gambino, Kirk D. Peterson, Jed H. Rankin | 2015-03-31 |
| 8912630 | Integrated circuit including thermal gate, related method and design structure | Jed H. Rankin, Dustin K. Slisher | 2014-12-16 |
| 8815669 | Metal gate structures for CMOS transistor devices having reduced parasitic capacitance | Jin Cai, Chengwen Pei, Ping-Chuan Wang | 2014-08-26 |
| 8815671 | Use of contacts to create differential stresses on devices | John J. Ellis-Monaghan, Jeffrey P. Gambino, Kirk D. Peterson, Jed H. Rankin | 2014-08-26 |
| 8741725 | Butted SOI junction isolation structures and devices and method of fabrication | Jeffrey B. Johnson, Shreesh Narasimha, Hasan M. Nayfeh, Viorel Ontalus | 2014-06-03 |
| 8709833 | Measuring current and resistance using combined diodes/resistor structure to monitor integrated circuit manufacturing process variations | Lyndon R. Logan, Edward J. Nowak, Jonathan K. Winslow, II | 2014-04-29 |
| 8686508 | Structures, methods and applications for electrical pulse anneal processes | Michel J. Abou-Khalil, Robert J. Gauthier, Jr., Tom C. Lee, Junjun Li, Souvick Mitra +1 more | 2014-04-01 |
| 8685817 | Metal gate structures for CMOS transistor devices having reduced parasitic capacitance | Jin Cai, Chengwen Pei, Ping-Chuan Wang | 2014-04-01 |
| 8652922 | Compact thermally controlled thin film resistors utilizing substrate contacts and methods of manufacture | Joseph M. Lukaitis, Jed H. Rankin, Dustin K. Slisher, Timothy D. Sullivan | 2014-02-18 |
| 8637871 | Asymmetric hetero-structure FET and method of manufacture | Brent A. Anderson, Jeffrey B. Johnson, Edward J. Nowak | 2014-01-28 |
| 8610211 | Semiconductor-on-insulator (SOI) structure with selectively placed sub-insulator layer void(s) and method of forming the SOI structure | Toshiharu Furukawa, Richard Q. Williams | 2013-12-17 |
| 8541864 | Compact thermally controlled thin film resistors utilizing substrate contacts and methods of manufacture | Joseph M. Lukaitis, Jed H. Rankin, Dustin K. Slisher, Timothy D. Sullivan | 2013-09-24 |
| 8530319 | Vertical silicide e-fuse | Ephrem G. Gebreselasie, Joseph M. Lukaitis, William R. Tonti, Ping-Chuan Wang | 2013-09-10 |
| 8486796 | Thin film resistors and methods of manufacture | David L. Harmon, Joseph M. Lukaitis, Stewart E. Rauch, III, Dustin K. Slisher, Jeffrey H. Sloan +2 more | 2013-07-16 |
| 8482075 | Structure and method for manufacturing asymmetric devices | Hasan M. Nayfeh, Andres Bryant, Arvind Kumar, Nivo Rovedo | 2013-07-09 |
| 8470682 | Methods and structures for increased thermal dissipation of thin film resistors | Brent A. Anderson, Jed H. Rankin | 2013-06-25 |