Issued Patents All Time
Showing 376–400 of 635 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9837394 | Self-aligned three dimensional chip stack and method for making the same | Carl Radens, Yiheng Xu, John H. Zhang | 2017-12-05 |
| 9837355 | Method for maximizing air gap in back end of the line interconnect through via landing modification | Benjamin D. Briggs, Christopher J. Penny, Michael Rizzolo | 2017-12-05 |
| 9837309 | Semiconductor via structure with lower electrical resistance | Baozhen Li, Kirk D. Peterson, Terry A. Spooner, Junli Wang | 2017-12-05 |
| 9837305 | Forming deep airgaps without flop over | Benjamin D. Briggs, Bartlet H. DeProspo, Huai Huang, Christopher J. Penny, Michael Rizzolo | 2017-12-05 |
| 9824982 | Structure and fabrication method for enhanced mechanical strength crack stop | Benjamin D. Briggs, Bartlet H. DeProspo, Huai Huang, Christopher J. Penny, Michael Rizzolo | 2017-11-21 |
| 9806018 | Copper interconnect structures | Wei Wang, Chih-Chao Yang | 2017-10-31 |
| 9793206 | Heterogeneous metallization using solid diffusion removal of metal interconnects | Benjamin D. Briggs, Bartlet H. DeProspo, Huai Huang, Christopher J. Penny, Michael Rizzolo | 2017-10-17 |
| 9786603 | Surface nitridation in metal interconnects | Roger A. Quon, Terry A. Spooner, Wei Wang, Chih-Chao Yang | 2017-10-10 |
| 9786554 | Self aligned conductive lines | Sean D. Burns, Anuja E. DeSilva, Nelson Felix, Sivananda K. Kanakasabapathy, Yann Mignot +3 more | 2017-10-10 |
| 9786551 | Trench structure for high performance interconnection lines of different resistivity and method of making same | John H. Zhang, Carl Radens, Yiheng Xu, Richard S. Wise | 2017-10-10 |
| 9779944 | Method and structure for cut material selection | Sean D. Burns, Matthew E. Colburn, Nelson Felix, Sivananda K. Kanakasabapathy, Yann Mignot +3 more | 2017-10-03 |
| 9778007 | Matching a spent firearm cartridge | Benjamin D. Briggs, Bartlet H. DeProspo, Michael Rizzolo | 2017-10-03 |
| 9773700 | Aligning conductive vias with trenches | Sean D. Burns, Matthew E. Colburn, Sivananda K. Kanakasabapathy, Yann Mignot, Christopher J. Penny +2 more | 2017-09-26 |
| 9768116 | Optimized wires for resistance or electromigration | Baozhen Li, Kirk D. Peterson | 2017-09-19 |
| 9761655 | Stacked planar capacitors with scaled EOT | Takashi Ando, Hemanth Jagannathan, Roger A. Quon | 2017-09-12 |
| 9761482 | Enhancement of iso-via reliability | Baozhen Li, Xiao Hu Liu, Kirk D. Peterson | 2017-09-12 |
| 9760817 | Security key system | Benjamin D. Briggs, Bartlet H. DeProspo, Michael Rizzolo | 2017-09-12 |
| 9758095 | Smartwatch blackbox | Benjamin D. Briggs, Leigh Anne H. Clevenger, Jonathan H. Connell, II, Nalini K. Ratha, Michael Rizzolo | 2017-09-12 |
| 9754891 | Low-temperature diffusion doping of copper interconnects independent of seed layer composition | Benjamin D. Briggs, Chao-Kun Hu, Takeshi Nogami, Deepika Priyadarshini, Michael Rizzolo | 2017-09-05 |
| 9754885 | Hybrid metal interconnects with a bamboo grain microstructure | Benjamin D. Briggs, Michael Rizzolo, Chih-Chao Yang | 2017-09-05 |
| 9754883 | Hybrid metal interconnects with a bamboo grain microstructure | Benjamin D. Briggs, Michael Rizzolo, Chih-Chao Yang | 2017-09-05 |
| 9741613 | Method for producing self-aligned line end vias and related device | John H. Zhang, Carl Radens | 2017-08-22 |
| 9741609 | Middle of line cobalt interconnection | Kangguo Cheng, Balasubramanian S. Pranatharthi Haran, John H. Zhang | 2017-08-22 |
| 9735029 | Metal fill optimization for self-aligned double patterning | Albert M. Chu, Ximeng Guan, Myung-Hee Na | 2017-08-15 |
| 9711507 | Separate N and P fin etching for reduced CMOS device leakage | Isabel Cristina Chu, Leigh Anne H. Clevenger, Mona A. Ebrish, Gauri Karve, Fee Li Lie +3 more | 2017-07-18 |