Issued Patents All Time
Showing 1,501–1,525 of 2,819 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9899495 | Vertical transistors with reduced bottom electrode series resistance | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2018-02-20 |
| 9899372 | Forming on-chip metal-insulator-semiconductor capacitor | Zhenxing Bi, Peng Xu, Chen Zhang | 2018-02-20 |
| 9892976 | Forming a hybrid channel nanosheet semiconductor structure | Peng Xu | 2018-02-13 |
| 9892973 | Stress memorization technique for strain coupling enhancement in bulk finFET device | Juntao Li, Chun-Chen Yeh | 2018-02-13 |
| 9892961 | Air gap spacer formation for nano-scale semiconductor devices | Thomas J. Haigh, Jr., Juntao Li, Eric G. Liniger, Sanjay C. Mehta, Son V. Nguyen +2 more | 2018-02-13 |
| 9892926 | Replacement low-k spacer | Xiuyu Cai, Ali Khakifirooz, Ruilong Xie | 2018-02-13 |
| 9892925 | Overhang hardmask to prevent parasitic epitaxial nodules at gate end during source drain epitaxy | Pouya Hashemi, Shogo Mochizuki, Alexander Reznicek | 2018-02-13 |
| 9892910 | Method and structure for forming a dense array of single crystalline semiconductor nanocrystals | Hong He, Juntao Li | 2018-02-13 |
| 9893181 | Uniform gate length in vertical field effect transistors | Peng Xu | 2018-02-13 |
| 9893169 | Fabrication of a vertical fin field effect transistor having a consistent channel width | Juntao Li | 2018-02-13 |
| 9893166 | Dummy gate formation using spacer pull down hardmask | Marc A. Bergendahl, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan | 2018-02-13 |
| 9893151 | Method and apparatus providing improved thermal conductivity of strain relaxed buffer | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2018-02-13 |
| 9893145 | On chip MIM capacitor | Theodorus E. Standaert | 2018-02-13 |
| 9893022 | Self-destructive circuits under radiation | Qing Cao, Fei Liu | 2018-02-13 |
| 9892978 | Forming a CMOS with dual strained channels | Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2018-02-13 |
| 9892975 | Adjacent strained <100> NFET fins and <110> PFET fins | Bruce B. Doris, Pouya Hashemi, Alexander Reznicek | 2018-02-13 |
| 9887198 | Semiconductor devices with sidewall spacers of equal thickness | Balasubramanian Pranatharthiharan, Soon-Cheon Seo | 2018-02-06 |
| 9887197 | Structure containing first and second vertically stacked nanosheets having different crystallographic orientations | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2018-02-06 |
| 9881937 | Preventing strained fin relaxation | Bruce B. Doris, Hong He, Sivananda K. Kanakasabapathy, Gauri Karve, Juntao Li +3 more | 2018-01-30 |
| 9881926 | Static random access memory (SRAM) density scaling by using middle of line (MOL) flow | Veeraraghavan S. Basker, Sivananda K. Kanakasabapathy, Theodorus E. Standaert, Junli Wang | 2018-01-30 |
| 9881998 | Stacked nanosheet field effect transistor device with substrate isolation | Juntao Li, Geng Wang, Qintao Zhang | 2018-01-30 |
| 9882005 | Fully depleted silicon-on-insulator device formation | Shawn P. Fetterolf, Ahmet S. Ozcan | 2018-01-30 |
| 9882024 | Epitaxial and silicide layer formation at top and bottom surfaces of semiconductor fins | Zuoguang Liu, Ruilong Xie, Tenko Yamashita | 2018-01-30 |
| 9882028 | Pitch split patterning for semiconductor devices | Lawrence A. Clevenger, Balasubramanian Pranatharthiharan, John H. Zhang | 2018-01-30 |
| 9882050 | Strained CMOS on strain relaxation buffer substrate | Juntao Li, Balasubramanian Pranatharthiharan | 2018-01-30 |