Issued Patents All Time
Showing 1,451–1,475 of 2,819 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9935101 | Vertical field effect transistor with uniform gate length | Xin Miao, Wenyu Xu, Chen Zhang | 2018-04-03 |
| 9935102 | Method and structure for improving vertical transistor | Zhenxing Bi, Juntao Li, Peng Xu | 2018-04-03 |
| 9935181 | FinFET having highly doped source and drain regions | Ali Khakifirooz, Alexander Reznicek, Dominic J. Schepis | 2018-04-03 |
| 9935180 | Fin cut for taper device | Ruilong Xie, Tenko Yamashita | 2018-04-03 |
| 9929060 | Porous silicon relaxation medium for dislocation free CMOS devices | Ramachandra Divakaruni, Jeehwan Kim, Juntao Li, Devendra K. Sadana | 2018-03-27 |
| 9929046 | Self-aligned contact cap | Peng Xu | 2018-03-27 |
| 9929266 | Method and structure for incorporating strain in nanosheet devices | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2018-03-27 |
| 9929256 | Fabrication of an isolated dummy fin between active vertical fins with tight fin pitch | Peng Xu | 2018-03-27 |
| 9929247 | Etch stop for airgap protection | Ruilong Xie, Tenko Yamashita | 2018-03-27 |
| 9929246 | Forming air-gap spacer for vertical field effect transistor | Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh | 2018-03-27 |
| 9929163 | Selective epitaxy growth for semiconductor devices with fin field-effect transistors (FinFET) | Veeraraghavan S. Basker, Ali Khakifirooz | 2018-03-27 |
| 9929145 | Bipolar transistor compatible with vertical FET fabrication | Brent A. Anderson, Terence B. Hook, Tak H. Ning | 2018-03-27 |
| 9929290 | Electrical and optical via connections on a same chip | Juntao Li, Chengwen Pei, Geng Wang, Joseph Ervin | 2018-03-27 |
| 9929270 | Gate all-around FinFET device and a method of manufacturing same | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2018-03-27 |
| 9923083 | Embedded endpoint fin reveal | Peng Xu | 2018-03-20 |
| 9923160 | Method of assembling carbon nanotubes of a semiconductor device via fringing field assisted dielectrophoresis | Qing Cao, Shu-Jen Han, Zhengwen Li, Fei Liu | 2018-03-20 |
| 9922886 | Silicon-germanium FinFET device with controlled junction | Pouya Hashemi, Kam-Leung Lee, Alexander Reznicek | 2018-03-20 |
| 9923055 | Inner spacer for nanosheet transistors | Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh | 2018-03-20 |
| 9917210 | FinFET transistor gate and epitaxy formation | Ruqiang Bao, Zhenxing Bi, Zheng Xu | 2018-03-13 |
| 9917199 | Method for reduced parasitic capacitance and contact resistance in extremely thin silicon-on-insulator (ETSOI) devices due to wrap-around structure of source/drain regions | Ramachandra Divakaruni | 2018-03-13 |
| 9917188 | Dielectric isolated fin with improved fin profile | Bruce B. Doris, Darsen D. Lu, Ali Khakifirooz, Kern Rim | 2018-03-13 |
| 9917179 | Stacked nanowire devices formed using lateral aspect ratio trapping | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2018-03-13 |
| 9917175 | Tapered vertical FET having III-V channel | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2018-03-13 |
| 9917162 | Fabrication of vertical field effect transistor structure with controlled gate length | Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh | 2018-03-13 |
| 9917154 | Strained and unstrained semiconductor device features formed on the same substrate | Juntao Li, Peng Xu | 2018-03-13 |