Issued Patents All Time
Showing 1,476–1,500 of 2,819 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9917152 | Nanosheet transistors on bulk material | Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh | 2018-03-13 |
| 9917106 | Embedded security circuit formed by directed self-assembly | Chi-Chun Liu | 2018-03-13 |
| 9917090 | Vertical antifuse structures | Juntao Li, Geng Wang, Qintao Zhang | 2018-03-13 |
| 9917082 | Approach to fabrication of an on-chip resistor with a field effect transistor | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2018-03-13 |
| 9917081 | Semiconductor device including finFET and fin varactor | Junli Wang, Ruilong Xie, Tenko Yamashita | 2018-03-13 |
| 9917052 | Method of fabricating anti-fuse for silicon on insulator devices | Ali Khakifirooz, Juntao Li | 2018-03-13 |
| 9917021 | Porous silicon relaxation medium for dislocation free CMOS devices | Ramachandra Divakaruni, Jeehwan Kim, Juntao Li, Devendra K. Sadana | 2018-03-13 |
| 9917015 | Dual channel material for finFET for high performance CMOS | Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2018-03-13 |
| 9911834 | Integrated strained stacked nanosheet FET | Ramachandra Divakaruni, Juntao Li, Xin Miao | 2018-03-06 |
| 9911656 | Wimpy device by selective laser annealing | Nicolas Loubet, Xin Miao, Alexander Reznicek | 2018-03-06 |
| 9911657 | Semiconductor device including finFET and fin varactor | Junli Wang, Ruilong Xie, Tenko Yamashita | 2018-03-06 |
| 9911662 | Forming a CMOS with dual strained channels | Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2018-03-06 |
| 9911739 | III-V FinFET CMOS with III-V and germanium-containing channel closely spaced | Ali Khakifirooz, Alexander Reznicek, Ghavam G. Shahidi | 2018-03-06 |
| 9911741 | Dual channel material for finFET for high performance CMOS | Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek | 2018-03-06 |
| 9905479 | Semiconductor devices with sidewall spacers of equal thickness | Balasubramanian Pranatharthiharan, Soon-Cheon Seo | 2018-02-27 |
| 9905469 | Method and structure for forming FinFET CMOS with dual doped STI regions | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2018-02-27 |
| 9905671 | Forming a gate contact in the active area | Ruilong Xie, Tenko Yamashita | 2018-02-27 |
| 9905663 | Fabrication of a vertical fin field effect transistor with a reduced contact resistance | Xin Miao, Wenyu Xu, Chen Zhang | 2018-02-27 |
| 9905643 | Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistors | Marc A. Bergendahl, Eric R. Miller, John R. Sporre, Sean Teehan | 2018-02-27 |
| 9899373 | Forming vertical transistors and metal-insulator-metal capacitors on the same chip | Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh | 2018-02-20 |
| 9899378 | Simultaneously fabricating a high voltage transistor and a finFET | Ali Khakifirooz, Alexander Reznicek, Charan V. Surisetty | 2018-02-20 |
| 9899383 | Forming gates with varying length using sidewall image transfer | Juntao Li, Geng Wang, Qintao Zhang | 2018-02-20 |
| 9899384 | Self aligned structure and method for high-K metal gate work function tuning | Bruce B. Doris, Ali Khakifirooz, Alexander Reznicek | 2018-02-20 |
| 9899391 | Metal trench capacitor and improved isolation and methods of manufacture | Roger A. Booth, Jr., Joseph Ervin, Chengwen Pei, Ravi M. Todi, Geng Wang | 2018-02-20 |
| 9899515 | Fabrication of a pair of vertical fin field effect transistors having a merged top source/drain | Xin Miao, Wenyu Xu, Chen Zhang | 2018-02-20 |