Issued Patents All Time
Showing 1,526–1,550 of 2,819 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9881839 | Forming a hybrid channel nanosheet semiconductor structure | Peng Xu | 2018-01-30 |
| 9876097 | Selectively formed gate sidewall spacer | Xin Miao, Wenyu Xu, Chen Zhang | 2018-01-23 |
| 9876015 | Tight pitch inverter using vertical transistors | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2018-01-23 |
| 9876009 | CMOS compatible fuse or resistor using self-aligned contacts | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2018-01-23 |
| 9875896 | Method for forming a strained semiconductor layer including replacing an etchable material formed under the strained semiconductor layer with a dielectric layer | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2018-01-23 |
| 9870952 | Formation of VFET and finFET | Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh | 2018-01-16 |
| 9870958 | Forming CMOSFET structures with different contact liners | Zuoguang Liu, Tenko Yamashita | 2018-01-16 |
| 9871118 | Semiconductor structure with an L-shaped bottom plate | Wilfried E. Haensch, Ali Khakifirooz, Davood Shahrjerdi | 2018-01-16 |
| 9871116 | Replacement metal gate structures | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2018-01-16 |
| 9871041 | Fabrication of vertical doped fins for complementary metal oxide semiconductor field effect transistors | Zuoguang Liu, Sanjay C. Mehta, Tenko Yamashita | 2018-01-16 |
| 9870989 | Electrical fuse and/or resistor structures | Veeraraghavan S. Basker, Ali Khakifirooz, Juntao Li | 2018-01-16 |
| 9870948 | Forming insulator fin structure in isolation region to support gate structures | Peng Xu | 2018-01-16 |
| 9865739 | Replacement metal gate structures | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2018-01-09 |
| 9865705 | Vertical field effect transistors with bottom source/drain epitaxy | Xin Miao, Wenyu Xu, Chen Zhang | 2018-01-09 |
| 9865598 | FinFET with uniform shallow trench isolation recess | Zhenxing Bi, Juntao Li, Peng Xu | 2018-01-09 |
| 9865587 | Method and structure for forming buried ESD with FinFETs | Nicolas Loubet, Xin Miao, Alexander Reznicek | 2018-01-09 |
| 9865509 | FinFET CMOS with Si NFET and SiGe PFET | Ramachandra Divakaruni, Jeehwan Kim | 2018-01-09 |
| 9865462 | Strain relaxed buffer layers with virtually defect free regions | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2018-01-09 |
| 9859172 | Bipolar transistor compatible with vertical FET fabrication | Brent A. Anderson, Terence B. Hook, Tak H. Ning | 2018-01-02 |
| 9859494 | Nanoparticle with plural functionalities, and method of forming the nanoparticle | Qing Cao, Zhengwen Li, Fei Liu | 2018-01-02 |
| 9859420 | Tapered vertical FET having III-V channel | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2018-01-02 |
| 9859409 | Single-electron transistor with wrap-around gate | Xin Miao, Wenyu Xu, Chen Zhang | 2018-01-02 |
| 9859389 | Sidewall protective layer for contact formation | Xin Miao, Wenyu Xu, Chen Zhang | 2018-01-02 |
| 9859388 | Uniform vertical field effect transistor spacers | Juntao Li | 2018-01-02 |
| 9859371 | Semiconductor device including a strain relief buffer | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2018-01-02 |