Issued Patents All Time
Showing 301–325 of 2,819 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11152478 | Vertical transistors with buried metal silicide bottom contact | Tak H. Ning, Alexander Reznicek | 2021-10-19 |
| 11152266 | Vertical tunneling field effect transistor with dual liner bottom spacer | Eric R. Miller, Marc A. Bergendahl, Sean Teehan, John R. Sporre | 2021-10-19 |
| 11152307 | Buried local interconnect | Lawrence A. Clevenger, Carl Radens, Junli Wang, John H. Zhang | 2021-10-19 |
| 11152213 | Transistor device with ultra low-k self aligned contact cap and ultra low-k spacer | — | 2021-10-19 |
| 11152377 | Nanosheet SRAM by SIT process | — | 2021-10-19 |
| 11152460 | High thermal budget compatible punch through stop integration using doped glass | Sanjay C. Mehta, Xin Miao, Chun-Chen Yeh | 2021-10-19 |
| 11145758 | Fully-depleted CMOS transistors with u-shaped channel | Robert H. Dennard, Bruce B. Doris, Terence B. Hook | 2021-10-12 |
| 11145743 | Transistor device having a comb-shaped channel region to increase the effective gate width | — | 2021-10-12 |
| 11145551 | FinFET devices | Veeraraghavan S. Basker, Theodoras E. Standaert, Junli Wang | 2021-10-12 |
| 11145677 | Fully depleted semiconductor-on-insulator transistors with different buried dielectric layer charges and different threshold voltages | Shawn P. Fetterolf | 2021-10-12 |
| 11145508 | Forming a fin cut in a hardmask | Zhenxing Bi, Juntao Li, Peng Xu | 2021-10-12 |
| 11139242 | Via-to-metal tip connections in multi-layer chips | Ruilong Xie, Chih-Chao Yang, Chi-Chun Liu | 2021-10-05 |
| 11139307 | Vertical field effect transistor including integrated antifuse | Juntao Li, Geng Wang, Qintao Zhang | 2021-10-05 |
| 11139399 | Vertical transistor with self-aligned gate | Juntao Li, Ruilong Xie, Chanro Park | 2021-10-05 |
| 11133308 | Uniform work function metal recess for vertical transistor complementary metal oxide semiconductor technology | Ruilong Xie, Muthumanickam Sankarapandian, Chanro Park | 2021-09-28 |
| 11131647 | Ion-sensitive field-effect transistor with sawtooth well to enhance sensitivity | Chanro Park, Juntao Li, Ruilong Xie | 2021-09-28 |
| 11127825 | Middle-of-line contacts with varying contact area providing reduced contact resistance | Chanro Park, Ruilong Xie, Hari Prasad Amanapu | 2021-09-21 |
| 11120991 | Lateral semiconductor nanotube with hexagonal shape | Juntao Li, Peng Xu, Choonghyun Lee | 2021-09-14 |
| 11121032 | Fabrication of self-aligned gate contacts and source/drain contacts directly above gate electrodes and source/drains | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2021-09-14 |
| 11121044 | Vertically stacked nanosheet CMOS transistor | Juntao Li, Zhenxing Bi | 2021-09-14 |
| 11121233 | Forming nanosheet transistor using sacrificial spacer and inner spacers | Julien Frougier, Nicolas Loubet | 2021-09-14 |
| 11121215 | iFinFET | Juntao Li, Chen Zhang, Xin Miao | 2021-09-14 |
| 11121318 | Tunable forming voltage for RRAM device | Dexin Kong, Juntao Li, Zheng Xu | 2021-09-14 |
| 11121232 | Stacked nanosheets with self-aligned inner spacers and metallic source/drain | Choonghyun Lee, Juntao Li | 2021-09-14 |
| 11107827 | Integration of split gate metal-oxide-nitride-oxide-semiconductor memory with vertical FET | Ruilong Xie, Julien Frougier | 2021-08-31 |