Issued Patents All Time
Showing 326–350 of 2,819 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11107731 | Self-aligned repaired top via | Ruilong Xie, Chih-Chao Yang, Carl Radens, Juntao Li | 2021-08-31 |
| 11107905 | Vertical field effect transistors with self aligned source/drain junctions | Xin Miao, Chen Zhang, Wenyu Xu | 2021-08-31 |
| 11105770 | Nanopore and DNA sensor employing nanopore | — | 2021-08-31 |
| 11107728 | Interconnects with tight pitch and reduced resistance | — | 2021-08-31 |
| 11101323 | RRAM cells in crossbar array architecture | Dexin Kong, Takashi Ando, Juntao Li | 2021-08-24 |
| 11101182 | Nanosheet transistors with different gate dielectrics and workfunction metals | Choonghyun Lee, Juntao Li, Peng Xu | 2021-08-24 |
| 11101217 | Buried power rail for transistor devices | Ruilong Xie, Alexander Reznicek, Junli Wang | 2021-08-24 |
| 11101322 | RRAM cells in crossbar array architecture | Dexin Kong, Takashi Ando, Juntao Li | 2021-08-24 |
| 11101181 | Junction formation in thick-oxide and thin-oxide vertical FETs on the same chip | Xin Miao, Wenyu Xu, Chen Zhang | 2021-08-24 |
| 11094883 | Structure and method to fabricate resistive memory with vertical pre-determined filament | Chanro Park, Ruilong Xie, Choonghyun Lee | 2021-08-17 |
| 11094823 | Stress induction in 3D device channel using elastic relaxation of high stress material | Nicolas Loubet, Xin Miao, Alexander Reznicek | 2021-08-17 |
| 11094824 | Forming a sacrificial liner for dual channel devices | Huiming Bu, Dechao Guo, Sivananda K. Kanakasabapathy, Peng Xu | 2021-08-17 |
| 11092551 | Staircase surface-enhanced raman scattering substrate | Chanro Park, Ruilong Xie, Juntao Li | 2021-08-17 |
| 11094781 | Nanosheet structures having vertically oriented and horizontally stacked nanosheets | Ruilong Xie, Huimei Zhou, Ardasheir Rahman | 2021-08-17 |
| 11094784 | Gate-all-around field effect transistor having stacked U shaped channels configured to improve the effective width of the transistor | Ruilong Xie, Julien Frougier, Chanro Park, Tenko Yamashita | 2021-08-17 |
| 11094798 | Vertical FET with symmetric junctions | Lan Yu, Xin Miao, Chen Zhang, Heng Wu | 2021-08-17 |
| 11088279 | Channel strain formation in vertical transport FETS with dummy stressor materials | Choonghyun Lee, Shogo Mochizuki, Juntao Li | 2021-08-10 |
| 11088260 | On-chip integrated temperature protection device based on gel electrolyte | Qing Cao, Zhengwen Li, Fei Liu | 2021-08-10 |
| 11087993 | Double replacement metal line patterning | Ruilong Xie, Chih-Chao Yang, Hsueh-Chung Chen | 2021-08-10 |
| 11088026 | Wimpy device by selective laser annealing | Nicolas Loubet, Xin Miao, Alexander Reznicek | 2021-08-10 |
| 11088247 | Method of fabrication of a semiconductor device including one or more nanostructures | Shay Reboh, Remi Coquand, Nicolas Loubet | 2021-08-10 |
| 11081400 | Fabrication of a pair of vertical fin field effect transistors having a merged top source/drain | Xin Miao, Wenyu Xu, Chen Zhang | 2021-08-03 |
| 11081482 | Fabrication of vertical fin field effect transistors having top air spacers and a self aligned top junction | Xin Miao, Wenyu Xu, Chen Zhang | 2021-08-03 |
| 11081172 | On-chip security key with phase change memory | Carl Radens, Ruilong Xie, Juntao Li | 2021-08-03 |
| 11081546 | Isolation structure for stacked vertical transistors | Juntao Li, Chen Zhang, Zhenxing Bi | 2021-08-03 |