Issued Patents All Time
Showing 376–400 of 2,819 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11043581 | Nanosheet channel-to-source and drain isolation | Marc A. Bergendahl, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan | 2021-06-22 |
| 11043451 | Electrical fuse and/or resistor structures | Veeraraghavan S. Basker, Ali Khakifirooz, Juntao Li | 2021-06-22 |
| 11043429 | Semiconductor fins with dielectric isolation at fin bottom | Peng Xu, Jay William Strane | 2021-06-22 |
| 11043411 | Integration of air spacer with self-aligned contact in transistor | Chanro Park, Ruilong Xie, Julien Frougier | 2021-06-22 |
| 11043493 | Stacked nanosheet complementary metal oxide semiconductor field effect transistor devices | Zhenxing Bi, Juntao Li | 2021-06-22 |
| 11038040 | Fin field effect transistor devices with robust gate isolation | — | 2021-06-15 |
| 11038015 | Non-planar field effect transistor devices with low-resistance metallic gate structures | Chen Zhang, Wenyu Xu, Xin Miao | 2021-06-15 |
| 11037725 | Manufacturing method for inductor with ferromagnetic cores | Juntao Li, Geng Wang, Qintao Zhang | 2021-06-15 |
| 11038106 | Phase change memory cell with a metal layer | Carl Radens, Juntao Li, Ruilong Xie | 2021-06-15 |
| 11031485 | Transistor with airgap spacer | Juntao Li, Ruilong Xie, Chanro Park | 2021-06-08 |
| 11031393 | III-V fins by aspect ratio trapping and self-aligned etch to remove rough epitaxy surface | Jeehwan Kim | 2021-06-08 |
| 11031297 | Multiple gate length vertical field-effect-transistors | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2021-06-08 |
| 11031295 | Gate cap last for self-aligned contact | Chanro Park, Ruilong Xie, Choonghyun Lee | 2021-06-08 |
| 11024739 | Fin field effect transistor including a single diffusion break with a multi-layer dummy gate | — | 2021-06-01 |
| 11024720 | Non-self aligned contact semiconductor devices | Ruilong Xie, Hari Prasad Amanapu, Chanro Park | 2021-06-01 |
| 11024711 | Nanosheet FET bottom isolation | Ruqiang Bao, Zhenxing Bi, Zheng Xu | 2021-06-01 |
| 11024547 | Method and structure for forming vertical transistors with shared gates and separate gates | Zhenxing Bi, Juntao Li, Peng Xu | 2021-06-01 |
| 11024539 | Self-aligned cut process for self-aligned via process window | Ruilong Xie, Chih-Chao Yang, Jing Guo | 2021-06-01 |
| 11023209 | On-chip hardware random number generator | — | 2021-06-01 |
| 11018254 | Fabrication of vertical fin transistor with multiple threshold voltages | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2021-05-25 |
| 11018240 | Vertical field effect transistor with reduced parasitic capacitance | Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh | 2021-05-25 |
| 11017999 | Method and structure for forming bulk FinFET with uniform channel height | Juntao Li, Xin Miao | 2021-05-25 |
| 11011704 | Forming RRAM cell structure with filament confinement | Juntao Li, Dexin Kong, Takashi Ando | 2021-05-18 |
| 11011638 | Transistor having airgap spacer around gate structure | Ruilong Xie, Julien Frougier, Chanro Park | 2021-05-18 |
| 11011626 | Fin field-effect transistor with reduced parasitic capacitance and reduced variability | Ruilong Xie, Juntao Li, Chanro Park | 2021-05-18 |