Issued Patents All Time
Showing 351–375 of 2,819 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11081172 | On-chip security key with phase change memory | Carl Radens, Ruilong Xie, Juntao Li | 2021-08-03 |
| 11075280 | Self-aligned gate and junction for VTFET | Zuoguang Liu, Oleg Gluschenkov, Muthumanickam Sankarapandian | 2021-07-27 |
| 11075299 | Transistor gate having tapered segments positioned above the fin channel | Eric R. Miller, Gauri Karve, Marc A. Bergendahl, Fee Li Lie, Sean Teehan | 2021-07-27 |
| 11075200 | Integrated device with vertical field-effect transistors and hybrid channels | Zhenxing Bi, Zheng Xu, Dexin Kong | 2021-07-27 |
| 11069679 | Reducing gate resistance in stacked vertical transport field effect transistors | Heng Wu, Chen Zhang, Tenko Yamashita, Joshua M. Rubin | 2021-07-20 |
| 11069680 | FinFET-based integrated circuits with reduced parasitic capacitance | Ruilong Xie, Juntao Li, Chanro Park | 2021-07-20 |
| 11069677 | Semiconductor device comprising metal-insulator-metal (MIM) capacitor | Chanro Park, Ruilong Xie, Juntao Li | 2021-07-20 |
| 11069800 | Single electron transistor with gap tunnel barriers | Xin Miao, Wenyu Xu, Chen Zhang | 2021-07-20 |
| 11069577 | Nanosheet transistors with different gate dielectrics and workfunction metals | Choonghyun Lee, Juntao Li, Peng Xu | 2021-07-20 |
| 11062937 | Dielectric isolation for nanosheet devices | Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh | 2021-07-13 |
| 11062959 | Inner spacer and junction formation for integrating extended-gate and standard-gate nanosheet transistors | Xin Miao, Wenyu Xu, Chen Zhang | 2021-07-13 |
| 11062960 | Shared contact trench comprising dual silicide layers and dual epitaxial layers for source/drain layers of NFET and PFET devices | Heng Wu, Junli Wang, Zuoguang Liu | 2021-07-13 |
| 11062965 | Flipped vertical field-effect-transistor | Xin Miao, Wenyu Xu, Chen Zhang | 2021-07-13 |
| 11063129 | Self-limiting fin spike removal | Choonghyun Lee, Juntao Li, Peng Xu | 2021-07-13 |
| 11063147 | Forming bottom source and drain extension on vertical transport FET (VTFET) | Shogo Mochizuki, Juntao Li, Choonghyun Lee | 2021-07-13 |
| 11056570 | Nanosheet transistor with dual inner airgap spacers | Ruilong Xie, Chun-Chen Yeh, Tenko Yamashita | 2021-07-06 |
| 11056399 | Source and drain EPI protective spacer during single diffusion break formation | Yao Yao, Andrew M. Greene, Veeraraghavan S. Basker, Zhenxing Bi, Ruilong Xie | 2021-07-06 |
| 11056537 | Self-aligned gate contact integration with metal resistor | Xin Miao, Richard A. Conti, Ruilong Xie | 2021-07-06 |
| 11049953 | Nanosheet transistor | Juntao Li, Heng Wu, Peng Xu | 2021-06-29 |
| 11049727 | Interleaved structure for molecular manipulation | Lawrence A. Clevenger, Shawn P. Fetterolf, Donald F. Canaperi | 2021-06-29 |
| 11049935 | Non-planar field effect transistor devices with low-resistance metallic gate structures | Chen Zhang, Wenyu Xu, Xin Miao | 2021-06-29 |
| 11049940 | Method and structure for forming silicon germanium finFET | Peng Xu, Juntao Li, Heng Wu | 2021-06-29 |
| 11044606 | User access verification | Shawn P. Fetterolf | 2021-06-22 |
| 11043634 | Confining filament at pillar center for memory devices | Dexin Kong, Takashi Ando, Juntao Li | 2021-06-22 |
| 11043581 | Nanosheet channel-to-source and drain isolation | Marc A. Bergendahl, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan | 2021-06-22 |