Issued Patents All Time
Showing 401–425 of 2,819 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11011622 | Closely packed vertical transistors with reduced contact resistance | Zhenxing Bi, Juntao Li, Peng Xu | 2021-05-18 |
| 11011617 | Formation of a partial air-gap spacer | Choonghyun Lee, Heng Wu, Peng Xu | 2021-05-18 |
| 11011432 | Vertical silicon/silicon-germanium transistors with multiple threshold voltages | Zhenxing Bi, Juntao Li, Peng Xu | 2021-05-18 |
| 11011411 | Semiconductor wafer having integrated circuits with bottom local interconnects | Chen Zhang, Xin Miao, Wenyu Xu | 2021-05-18 |
| 11004944 | Gate cut device fabrication with extended height gates | Andrew M. Greene, John R. Sporre, Peng Xu | 2021-05-11 |
| 11004856 | Stacked vertical transistor memory cell with epi connections | Chen Zhang, Tenko Yamashita, Heng Wu | 2021-05-11 |
| 11004751 | Vertical transistor having reduced edge fin variation | Juntao Li, Dexin Kong, Zhenxing Bi | 2021-05-11 |
| 11004737 | Field effect device with reduced capacitance and resistance in source/drain contacts at reduced gate pitch | Chi-Chun Liu, Peng Xu | 2021-05-11 |
| 10998441 | Strained silicon complementary metal oxide semiconductor including a silicon containing tensile n-type fin field effect transistor and silicon containing compressive p-type fin field effect transistor formed using a dual relaxed substrate | Nicolas Loubet, Xin Miao, Alexander Reznicek | 2021-05-04 |
| 10998424 | Vertical metal-air transistor | Juntao Li, Ruilong Xie, Chanro Park | 2021-05-04 |
| 10998242 | Semiconductor device including dual trench epitaxial dual-liner contacts | Veeraraghavan S. Basker, Theodoras E. Standaert, Junli Wang | 2021-05-04 |
| 10998240 | Fabrication of a vertical fin field effect transistor with reduced dimensional variations | — | 2021-05-04 |
| 10998230 | Fabrication of self-aligned gate contacts and source/drain contacts directly above gate electrodes and source/drains | Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang | 2021-05-04 |
| 10998229 | Transistor with improved self-aligned contact | Zhenxing Bi, Juntao Li, Dexin Kong | 2021-05-04 |
| 10991823 | Fabrication of vertical fin transistor with multiple threshold voltages | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2021-04-27 |
| 10991808 | Steep-switch field effect transistor with integrated bi-stable resistive system | Julien Frougier, Nicolas Loubet, Ruilong Xie, Daniel Chanemougame, Ali Razavieh | 2021-04-27 |
| 10991798 | Replacement sacrificial nanosheets having improved etch selectivity | Wenyu Xu, Chen Zhang, Xin Miao | 2021-04-27 |
| 10991584 | Methods and structures for cutting lines or spaces in a tight pitch structure | Peng Xu, Choonghyun Lee, Juntao Li | 2021-04-27 |
| 10985315 | Resistive random-access memory | Choonghyun Lee, Juntao Li, Peng Xu | 2021-04-20 |
| 10985279 | Source and drain epitaxy and isolation for gate structures | Juntao Li, Peng Xu, Zhenxing Bi | 2021-04-20 |
| 10985274 | Reduction of top source/drain external resistance and parasitic capacitance in vertical transistors | Choonghyun Lee, Juntao Li, Shogo Mochizuki | 2021-04-20 |
| 10985250 | Gate cut device fabrication with extended height gates | Andrew M. Greene, John R. Sporre, Peng Xu | 2021-04-20 |
| 10985236 | Tunable on-chip nanosheet resistor | Zhenxing Bi, Wei Wang, Zheng Xu | 2021-04-20 |
| 10985161 | Single diffusion break isolation for gate-all-around field-effect transistor devices | Wenyu Xu, Xin Miao, Chen Zhang | 2021-04-20 |
| 10985064 | Buried power and ground in stacked vertical transport field effect transistors | Chen Zhang, Heng Wu, Tenko Yamashita | 2021-04-20 |