Issued Patents All Time
Showing 251–275 of 2,819 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11251288 | Nanosheet transistor with asymmetric gate stack | Ruilong Xie, Carl Radens, Juntao Li, Dechao Guo, Tao Li +1 more | 2022-02-15 |
| 11251280 | Strained nanowire transistor with embedded epi | Heng Wu, Chen Zhang, Xin Miao, Lan Yu | 2022-02-15 |
| 11251267 | Vertical transistors with multiple gate lengths | Zhenxing Bi, Peng Xu, Zheng Xu | 2022-02-15 |
| 11244869 | Fabrication of logic devices and power devices on the same substrate | Juntao Li, Liying Jiang, John G. Gaudiello | 2022-02-08 |
| 11244864 | Reducing parasitic capacitance within semiconductor devices | Ruilong Xie, Reinaldo Vega, Alexander Reznicek | 2022-02-08 |
| 11239418 | Memory device having a ring heater | — | 2022-02-01 |
| 11239342 | Vertical transistors having improved control of top source or drain junctions | Ruilong Xie, Tenko Yamashita, Chun-Chen Yeh | 2022-02-01 |
| 11239165 | Method of forming an interconnect structure with enhanced corner connection | Ruilong Xie, Christopher J. Waskiewicz, Chih-Chao Yang | 2022-02-01 |
| 11233091 | Resistive memory cell having a single fin | — | 2022-01-25 |
| 11227937 | Uniform interfacial layer on vertical fin sidewalls of vertical transport field-effect transistors | Shogo Mochizuki, Choonghyun Lee, Juntao Li | 2022-01-18 |
| 11221359 | Determining device operability via metal-induced layer exchange | Dexin Kong | 2022-01-11 |
| 11217680 | Vertical field-effect transistor with T-shaped gate | Yi Song, Juntao Li, Huimei Zhou, Ardasheir Rahman | 2022-01-04 |
| 11211452 | Transistor having stacked source/drain regions with formation assistance regions and multi-region wrap-around source/drain contacts | Ruilong Xie, Reinaldo Vega, Chanro Park, Juntao Li | 2021-12-28 |
| 11211462 | Using selectively formed cap layers to form self-aligned contacts to source/drain regions | Chanro Park, Choonghyun Lee, Ruilong Xie | 2021-12-28 |
| 11211291 | Via formation with robust hardmask removal | Ruilong Xie, Christopher J. Waskiewicz, Chih-Chao Yang | 2021-12-28 |
| 11205590 | Self-aligned contacts for MOL | Su Chen Fan, Adra Carr, Ruilong Xie | 2021-12-21 |
| 11205592 | Self-aligned top via structure | Ruilong Xie, Cheng Chi, Chih-Chao Yang | 2021-12-21 |
| 11201089 | Robust low-k bottom spacer for VFET | Hiroaki Niimi, Pietro Montanini | 2021-12-14 |
| 11201231 | Silicon germanium alloy fins with reduced defects | Hong He, Juntao Li | 2021-12-14 |
| 11196001 | 3D ReRAM formed by metal-assisted chemical etching with replacement wordline and wordline separation | Xin Miao, Wenyu Xu, Chen Zhang | 2021-12-07 |
| 11196575 | On-chipset certification to prevent spy chip | — | 2021-12-07 |
| 11195745 | Forming single and double diffusion breaks for fin field-effect transistor structures | Juntao Li, Ruilong Xie, Junli Wang | 2021-12-07 |
| 11195746 | Nanosheet transistor with self-aligned dielectric pillar | Ruilong Xie, Julien Frougier | 2021-12-07 |
| 11195753 | Tiered-profile contact for semiconductor | Kisik Choi | 2021-12-07 |
| 11195912 | Inner spacer for nanosheet transistors | Choonghyun Lee, Juntao Li, Peng Xu | 2021-12-07 |