Issued Patents All Time
Showing 226–250 of 2,819 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11355649 | Nanosheet transistor having abrupt junctions between the channel nanosheets and the source/drain extension regions | Choonghyun Lee, Juntao Li, Shogo Mochizuki | 2022-06-07 |
| 11355644 | Vertical field effect transistors with self aligned contacts | Yi Song, Juntao Li | 2022-06-07 |
| 11355588 | Strained and unstrained semiconductor device features formed on the same substrate | Juntao Li, Peng Xu | 2022-06-07 |
| 11349001 | Replacement gate cross-couple for static random-access memory scaling | Ruilong Xie, Carl Radens, Veeraraghavan S. Basker, Juntao Li | 2022-05-31 |
| 11342230 | Homogeneous densification of fill layers for controlled reveal of vertical fins | Choonghyun Lee, Juntao Li, Heng Wu, Peng Xu | 2022-05-24 |
| 11335773 | Trench contact resistance reduction | Zhenxing Bi, Juntao Li, Peng Xu | 2022-05-17 |
| 11329143 | Nanosheet transistors with thin inner spacers and tight pitch gate | Choonghyun Lee, Juntao Li, Peng Xu | 2022-05-10 |
| 11329001 | Embedded chip identification formed by directed self-assembly | Chi-Chun Liu | 2022-05-10 |
| 11322588 | Contact source/drain resistance | Fee Li Lie, Choonghyun Lee, Hemanth Jagannathan, Oleg Gluschenkov | 2022-05-03 |
| 11322402 | Self-aligned top via scheme | Ruilong Xie, Chih-Chao Yang, Carl Radens, Juntao Li | 2022-05-03 |
| 11316015 | Silicon germanium FinFET with low gate induced drain leakage current | Shogo Mochizuki, Choonghyun Lee, Juntao Li | 2022-04-26 |
| 11315836 | Two-dimensional vertical fins | — | 2022-04-26 |
| 11315799 | Back end of line structures with metal lines with alternating patterning and metallization schemes | Ruilong Xie, Chanro Park, Chih-Chao Yang, Juntao Li | 2022-04-26 |
| 11309397 | Contact over active gate employing a stacked spacer | — | 2022-04-19 |
| 11302799 | Method and structure for forming a vertical field-effect transistor | Peng Xu, Choonghyun Lee, Juntao Li | 2022-04-12 |
| 11296226 | Transistor having wrap-around source/drain contacts and under-contact spacers | Yi Song, Praveen Joseph, Andrew M. Greene | 2022-04-05 |
| 11295985 | Forming a backside ground or power plane in a stacked vertical transport field effect transistor | Chen Zhang, Tenko Yamashita, Lawrence A. Clevenger | 2022-04-05 |
| 11282838 | Stacked gate structures | Chen Zhang, Dechao Guo, Junli Wang, Ruilong Xie, Juntao Li +5 more | 2022-03-22 |
| 11282961 | Enhanced bottom dielectric isolation in gate-all-around devices | Julien Frougier, Andrew M. Greene, Ruilong Xie | 2022-03-22 |
| 11276781 | Bottom source/drain for fin field effect transistors | Heng Wu, Shogo Mochizuki, Gen Tsutsui | 2022-03-15 |
| 11276612 | Hybrid-channel nano-sheet FETS | Zhenxing Bi, Peng Xu, Wenyu Xu | 2022-03-15 |
| 11270935 | Metallization layer formation process | Ruilong Xie, Chih-Chao Yang, Jing Guo | 2022-03-08 |
| 11270768 | Failure prevention of chip power network | Zheng Xu, Dexin Kong, Juntao Li | 2022-03-08 |
| 11264481 | Self-aligned source and drain contacts | Chanro Park, Ruilong Xie, Juntao Li | 2022-03-01 |
| 11257934 | Fin field-effect transistors with enhanced strain and reduced parasitic capacitance | Juntao Li, Choonghyun Lee, Shogo Mochizuki | 2022-02-22 |