Issued Patents All Time
Showing 126–150 of 164 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7217968 | Recessed gate for an image sensor | John J. Ellis-Monaghan, Mark D. Jaffe, Jerome B. Lasky | 2007-05-15 |
| 7205627 | Image sensor cells | John J. Ellis-Monaghan, Jeffrey P. Gambino, Mark D. Jaffe, Richard J. Rassel | 2007-04-17 |
| 7205591 | Pixel sensor cell having reduced pinning layer barrier potential and method thereof | Andres Bryant, John J. Ellis-Monaghan, Jeffrey P. Gambino, Mark D. Jaffe, Jerome B. Lasky +1 more | 2007-04-17 |
| 7194706 | Designing scan chains with specific parameter sensitivities to identify process defects | Greg Bazan, John M. Cohn, Matthew S. Grady, Leendert M. Huisman, Mark D. Jaffe +5 more | 2007-03-20 |
| 7193289 | Damascene copper wiring image sensor | Jeffrey P. Gambino, Mark D. Jaffe, Robert K. Leidy, Anthony K. Stamper | 2007-03-20 |
| 7186573 | Flip FERAM cell and method to form same | Charles T. Black, Alfred Grill, Randy W. Mann, Deborah A. Neumayer, Wilbur D. Pricer +2 more | 2007-03-06 |
| 7163864 | Method of fabricating semiconductor side wall fin | Paul D. Agnello, Arne Ballantine, Rama Divakaruni, Erin C. Jones, Edward J. Nowak +1 more | 2007-01-16 |
| 7141836 | Pixel sensor having doped isolation structure sidewall | Mark D. Jaffe, Robert K. Leidy | 2006-11-28 |
| 7129130 | Out of the box vertical transistor for eDRAM on SOI | Gary B. Bronner, Dureseti Chidambarrao, Ramachandra Divakaruni, Carl Radens | 2006-10-31 |
| 7112845 | Double gate trench transistor | Paul D. Agnello, Arne Ballantine, Rama Divakaruni, Erin C. Jones, Jed H. Rankin | 2006-09-26 |
| 7098067 | Masked sidewall implant for image sensor | Mark D. Jaffe, Arthur Paul Johnson, Robert K. Leidy, Jeffrey C. Maling | 2006-08-29 |
| 7089514 | Defect diagnosis for semiconductor integrated circuits | Greg Bazan, John M. Cohn, Francis Gravel, Leendert M. Huisman, Phillip J. Nigh +4 more | 2006-08-08 |
| 7009237 | Out of the box vertical transistor for eDRAM on SOI | Gary B. Bronner, Dureseti Chidambarrao, Ramachandra Divakaruni, Carl Radens | 2006-03-07 |
| 6960744 | Electrically tunable on-chip resistor | Anthony K. Stamper | 2005-11-01 |
| 6858889 | Polysilicon capacitor having large capacitance and low resistance | John A. Bracchitta, Jed H. Rankin, Anthony K. Stamper | 2005-02-22 |
| 6797553 | Method for making multiple threshold voltage FET using multiple work-function gate materials | Arne Ballantine, Ramachandra Divakaruni, Jeffrey B. Johnson, Erin C. Jones, Hon-Sum Philip Wong | 2004-09-28 |
| 6756637 | Method of controlling floating body effects in an asymmetrical SOI device | Michael Hargrove, Lyndon R. Logan, Isabel Yang | 2004-06-29 |
| 6670255 | Method of fabricating lateral diodes and bipolar transistors | Jeffrey P. Gambino, Peter B. Gray, Anthony K. Stamper | 2003-12-30 |
| 6660664 | Structure and method for formation of a blocked silicide resistor | Arne Ballantine, Matthew D. Gallagher, Peter J. Geiss, Jeffrey D. Gilbert, Shwu-Jen Jeng +6 more | 2003-12-09 |
| 6660596 | Double planar gated SOI MOSFET structure | John A. Bracchitta, John J. Ellis-Monaghan, Jerome B. Lasky, Effendi Leobandung, Kirk D. Peterson +1 more | 2003-12-09 |
| 6653710 | Fuse structure with thermal and crack-stop protection | Edward P. Maciejewski, Peter Smeys, Anthony K. Stamper | 2003-11-25 |
| 6590259 | Semiconductor device of an embedded DRAM on SOI substrate | Ramachandra Divakaruni, Jeffrey P. Gambino, Jack A. Mandelman | 2003-07-08 |
| 6563131 | Method and structure of a dual/wrap-around gate field effect transistor | Paul D. Agnello, Arne Ballantine, Christopher S. Putnam, Jed H. Rankin | 2003-05-13 |
| 6555859 | Flip FERAM cell and method to form same | Charles T. Black, Alfred Grill, Randy W. Mann, Deborah A. Neumayer, Wilbur D. Pricer +2 more | 2003-04-29 |
| 6483156 | Double planar gated SOI MOSFET structure | John A. Bracchitta, John J. Ellis-Monaghan, Jerome B. Lasky, Effendi Leobandung, Kirk D. Peterson +1 more | 2002-11-19 |