Issued Patents All Time
Showing 76–100 of 128 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6395594 | Method for simultaneously forming a storage-capacitor electrode and interconnect | David E. Kotecki, Carl Radens, Jeffrey P. Gambino | 2002-05-28 |
| 6388294 | Integrated circuit using damascene gate structure | Carl Radens, Mary E. Weybright | 2002-05-14 |
| 6369419 | Self-aligned near surface strap for high density trench DRAMS | Ramachandra Divakaruni, Jochen Beintner, Jack A. Mandelman, Ulrike Gruening, Johann Alsmeier | 2002-04-09 |
| 6348374 | Process for 4F2 STC cell having vertical MOSFET and buried-bitline conductor structure | Satish D. Athavale, Ramachandra Divakaruni, Ulrike Gruening, Jack A. Mandelman, Carl Radens | 2002-02-19 |
| 6344389 | Self-aligned damascene interconnect | Jeffrey P. Gambino, Carl Radens | 2002-02-05 |
| 6339001 | Formulation of multiple gate oxides thicknesses without exposing gate oxide or silicon surface to photoresist | Jeffrey P. Gambino | 2002-01-15 |
| 6320215 | Crystal-axis-aligned vertical side wall device | Ulrike Gruening, Jack A. Mandelman, Carl Radens | 2001-11-20 |
| 6281064 | Method for providing dual work function doping and protective insulating cap | Jack A. Mandelman, Ramachandra Divakaruni | 2001-08-28 |
| 6265308 | Slotted damascene lines for low resistive wiring lines for integrated circuit | Greg Costrini, Carl Radens, Rainer Florian Schnabel | 2001-07-24 |
| 6258689 | Low resistance fill for deep trench capacitor | Jeffrey P. Gambino, Jack A. Mandelman, Rick L. Mohler, Carl Radens, William R. Tonti | 2001-07-10 |
| 6242770 | Diode connected to a magnetic tunnel junction and self aligned with a metallic conductor and method for forming the same | Stephen M. Gates, Roy E. Scheuerlein | 2001-06-05 |
| 6214686 | Spatially offset deep trenches for high density DRAMS | Ramachandra Divakaruni | 2001-04-10 |
| 6201272 | Method for simultaneously forming a storage-capacitor electrode and interconnect | David E. Kotecki, Carl Radens, Jeffrey P. Gambino | 2001-03-13 |
| 6200834 | Process for fabricating two different gate dielectric thicknesses using a polysilicon mask and chemical mechanical polishing (CMP) planarization | Jeffrey P. Gambino, Carl Radens | 2001-03-13 |
| 6197632 | Method for dual sidewall oxidation in high density, high performance DRAMS | Rama Divakaruni, Scott D. Halle, Dale W. Martin, Rajesh Rengarajan, Mary E. Weybright | 2001-03-06 |
| 6194301 | Method of fabricating an integrated circuit of logic and memory using damascene gate structure | Carl Radens, Mary E. Weybright | 2001-02-27 |
| 6190959 | Semiconductor memory array having sublithographic spacing between adjacent trenches and method for making the same | Jack A. Mandelman, Donald J. Samuels | 2001-02-20 |
| 6180972 | Buried, implanted plate for DRAM trench storage capacitors | Wilfried Hansch, Wendell P. Noble | 2001-01-30 |
| 6177696 | Integration scheme enhancing deep trench capacitance in semiconductor integrated circuit devices | Laertis Economikos, Rajarao Jammy, Byeongju Park, Carl Radens, Martin Schrems | 2001-01-23 |
| 6174762 | Salicide device with borderless contact | Jeffrey P. Gambino, Louis L. Hsu, Jack A. Mandelman, Carl Radens, William R. Tonti | 2001-01-16 |
| 6174756 | Spacers to block deep junction implants and silicide formation in integrated circuits | Jeffrey P. Gambino, Johann Alsmeier | 2001-01-16 |
| 6140208 | Shallow trench isolation (STI) with bilayer of oxide-nitride for VLSI applications | Farid Agahi, Bertrand Flietner, Erwin Hammerl, Herbert L. Ho, Radhika Srinivasan | 2000-10-31 |
| 6124199 | Method for simultaneously forming a storage-capacitor electrode and interconnect | Jeffrey P. Gambino, David E. Kotecki, Carl Radens | 2000-09-26 |
| 6110792 | Method for making DRAM capacitor strap | Carl Radens, Juergen Wittmann | 2000-08-29 |
| 6107135 | Method of making a semiconductor memory device having a buried plate electrode | Richard L. Kleinhenz, Junichiro Iba | 2000-08-22 |