Issued Patents All Time
Showing 101–125 of 128 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6087225 | Method for dual gate oxide dual workfunction CMOS | Badih El-Kareh, Stanley E. Schuster | 2000-07-11 |
| 6084276 | Threshold voltage tailoring of corner of MOSFET device | Jeffrey P. Gambino, Jack A. Mandelman, Larry Nesbit | 2000-07-04 |
| 6063657 | Method of forming a buried strap in a DRAM | Ramachandra Divakaruni | 2000-05-16 |
| 6037194 | Method for making a DRAM cell with grooved transfer device | Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak, Jack A. Mandelman +1 more | 2000-03-14 |
| 6034877 | Semiconductor memory array having sublithographic spacing between adjacement trenches and method for making the same | Jack A. Mandelman, Donald J. Samuels | 2000-03-07 |
| 6028004 | Process for controlling the height of a stud intersecting an interconnect | Jeffrey P. Gambino | 2000-02-22 |
| 6014310 | High dielectric TiO.sub.2 -SiN composite films for memory applications | Stephan A. Cohen, David M. Dobuzinsky, Jeffrey P. Gambino, Herbert L. Ho, Karen P. Madden | 2000-01-11 |
| 5994202 | Threshold voltage tailoring of the corner of a MOSFET device | Jeffrey P. Gambino, Jack A. Mandelman, Larry Nesbit | 1999-11-30 |
| 5945707 | DRAM cell with grooved transfer device | Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak, Jack A. Mandelman +1 more | 1999-08-31 |
| 5937289 | Providing dual work function doping | Jeffrey P. Gambino, Jack A. Mandelman, Carl Radens, William R. Tonti | 1999-08-10 |
| 5923991 | Methods to prevent divot formation in shallow trench isolation areas | Jeffrey P. Gambino, Larry Nesbit | 1999-07-13 |
| 5908310 | Method to form a buried implanted plate for DRAM trench storage capacitors | Wilfried Hansch, Wendell P. Noble | 1999-06-01 |
| 5876788 | High dielectric TiO.sub.2 -SiN composite films for memory applications | Stephan A. Cohen, David M. Dobuzinsky, Jeffrey P. Gambino, Herbert L. Ho, Karen P. Madden | 1999-03-02 |
| 5792703 | Self-aligned contact wiring process for SI devices | Jeffrey P. Gambino | 1998-08-11 |
| 5766971 | Oxide strip that improves planarity | David C. Ahlgren, Wesley C. Natzle, Erick G. Walton, Chienfan Yu | 1998-06-16 |
| 5606188 | Fabrication process and structure for a contacted-body silicon-on-insulator dynamic random access memory | John K. DeBrosse, Jack A. Mandelman | 1997-02-25 |
| 5606202 | Planarized gate conductor on substrates with above-surface isolation | Jack A. Mandelman | 1997-02-25 |
| 5538592 | Non-random sub-lithography vertical stack capacitor | Bomy Chen, Son V. Nguyen | 1996-07-23 |
| 5525531 | SOI DRAM with field-shield isolation | John K. DeBrosse, Jack A. Mandelman | 1996-06-11 |
| 5508219 | SOI DRAM with field-shield isolation and body contact | John K. DeBrosse, Jack A. Mandelman | 1996-04-16 |
| 5362663 | Method of forming double well substrate plate trench DRAM cell array | Sang Hoo Dhong, Wei Hwang | 1994-11-08 |
| 5360758 | Self-aligned buried strap for trench type DRAM cells | John K. DeBrosse, Donald M. Kenney | 1994-11-01 |
| 5321647 | Semiconductor memory device and operational method with reduced well noise | Sang Hoo Dhong | 1994-06-14 |
| 5300800 | Low leakage substrate plate DRAM cell | Sang Hoo Dhong, Wei Hwang | 1994-04-05 |
| 5253202 | Word line driver circuit for dynamic random access memories | Sang Hoo Dhong, Wei Hwang | 1993-10-12 |