GB

Gary B. Bronner

IBM: 80 patents #845 of 70,183Top 2%
RA Rambus: 25 patents #85 of 549Top 20%
HL Hefei Reliance Memory Limited: 19 patents #3 of 28Top 15%
Infineon Technologies Ag: 5 patents #3,160 of 7,486Top 45%
SA Siemens Aktiengesellschaft: 2 patents #6,658 of 22,248Top 30%
SM Siemens Microelectronics: 1 patents #5 of 40Top 15%
CR Cryptography Research: 1 patents #44 of 64Top 70%
KT Kabushiki Kaisha Toshiba: 1 patents #13,537 of 21,451Top 65%
📍 Los Altos, CA: #40 of 3,651 inventorsTop 2%
🗺 California: #1,366 of 386,348 inventorsTop 1%
Overall (All Time): #8,679 of 4,157,543Top 1%
128
Patents All Time

Issued Patents All Time

Showing 51–75 of 128 patents

Patent #TitleCo-InventorsDate
7439568 Vertical body-contacted SOI transistor Kangguo Cheng, Ramachandra Divakaruni, Carl Radens 2008-10-21
7129130 Out of the box vertical transistor for eDRAM on SOI James W. Adkisson, Dureseti Chidambarrao, Ramachandra Divakaruni, Carl Radens 2006-10-31
7037794 Raised STI process for multiple gate ox and sidewall protection on strained Si/SGOI structure with elevated source/drain Jochen Beintner, Ramachandra Divakaruni, Byeong Y. Kim 2006-05-02
7009237 Out of the box vertical transistor for eDRAM on SOI James W. Adkisson, Dureseti Chidambarrao, Ramachandra Divakaruni, Carl Radens 2006-03-07
6974991 DRAM cell with buried collar and self-aligned buried strap Kangguo Cheng, Ramachandra Divkaruni, Carl Radens, Oleg Gluschenkov 2005-12-13
6808981 Method for fabricating 6F2 trench DRAM cell with double-gated vertical MOSFET and self-aligned STI Jack A. Mandelman, Ramachandra Divakaruni, Carl Radens 2004-10-26
6767789 Method for interconnection between transfer devices and storage capacitors in memory cells and device formed thereby David V. Horak, Toshiharu Furukawa, Jack A. Mandelman 2004-07-27
6759291 Self-aligned near surface strap for high density trench DRAMS Ramachandra Divakaruni, Jochen Beintner, Jack A. Mandelman, Ulrike Gruening, Johann Alsmeier 2004-07-06
6727141 DRAM having offset vertical transistors and method Ramachandra Divakaruni, Byeong Y. Kim, Jack A. Mandelman 2004-04-27
6656807 Grooved planar DRAM transfer device using buried pocket Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak, Jack A. Mandelman 2003-12-02
6638815 Formation of self-aligned vertical connector Ramachandra Divakaruni 2003-10-28
6614074 Grooved planar DRAM transfer device using buried pocket Toshiharu Furukawa, Mark C. Hakey, Steven J. Holmes, David V. Horak, Jack A. Mandelman 2003-09-02
6573137 Single sided buried strap Ramachandra Divakaruni, Jack A. Mandelman, Wolfgang Bergner, Ulrike Gruening, Stephan Kudelka +5 more 2003-06-03
6570208 6F2 Trench EDRAM cell with double-gated vertical MOSFET and self-aligned STI Jack A. Mandelman, Ramachandra Divakaruni, Carl Radens 2003-05-27
6566177 Silicon-on-insulator vertical array device trench capacitor DRAM Carl Radens, Tze-Chiang Chen, Bijan Davari, Jack A. Mandelman, Dan Moy +3 more 2003-05-20
6562634 Diode connected to a magnetic tunnel junction and self aligned with a metallic conductor and method of forming the same Stephen M. Gates, Roy E. Scheuerlein 2003-05-13
6548357 Modified gate processing for optimized definition of array and logic devices on same chip Mary E. Weybright, Richard A. Conti, Ramachandra Divakaruni, Jeffrey P. Gambino, Peter D. Hoh +1 more 2003-04-15
6538295 Salicide device with borderless contact Jeffrey P. Gambino, Louis L. Hsu, Jack A. Mandelman, Carl Radens, William R. Tonti 2003-03-25
6501117 Static self-refreshing DRAM structure and operating mode Carl Radens, Ramachandra Divakaruni, Jack A. Mandelman 2002-12-31
6495876 DRAM strap: hydrogen annealing for improved strap resistance in high density trench DRAMS Ramachandra Divakaruni, Yoichi Takegawa 2002-12-17
6429474 Storage-capacitor electrode and interconnect Jeffrey P. Gambino, David E. Kotecki, Carl Radens 2002-08-06
6426252 Silicon-on-insulator vertical array DRAM cell with self-aligned buried strap Carl Radens, Tze-Chiang Chen, Bijan Davari, Jack A. Mandelman, Dan Moy +3 more 2002-07-30
6426526 Single sided buried strap Ramachandra Divakaruni, Jack A. Mandelman, Carl Radens 2002-07-30
6426251 Process for manufacturing a crystal axis-aligned vertical side wall device Ulrike Gruening, Jack A. Mandelman, Carl Radens 2002-07-30
6403423 Modified gate processing for optimized definition of array and logic devices on same chip Mary E. Weybright, Richard A. Conti, Ramachandra Divakaruni, Jeffrey P. Gambino, Peter D. Hoh +1 more 2002-06-11