Issued Patents All Time
Showing 25 most recent of 189 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7883962 | Trench DRAM cell with vertical device and buried word lines | — | 2011-02-08 |
| 7785961 | Trench DRAM cell with vertical device and buried word lines | — | 2010-08-31 |
| 7488641 | Trench DRAM cell with vertical device and buried word lines | — | 2009-02-10 |
| 7282400 | Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction | Leonard Forbes, Alan R. Reinberg | 2007-10-16 |
| 7271467 | Multiple oxide thicknesses for merged memory and logic applications | Leonard Forbes | 2007-09-18 |
| 7232713 | Methods of forming interconnect lines | — | 2007-06-19 |
| 7223678 | Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor | Leonard Forbes | 2007-05-29 |
| 7217606 | Method of forming vertical sub-micron CMOS transistors on (110), (111), (311), (511), and higher order surfaces of bulk, soi and thin film structures | Leonard Forbes, Alan R. Reinberg | 2007-05-15 |
| 7176087 | Methods of forming electrical connections | — | 2007-02-13 |
| 7105386 | High density SRAM cell with latched vertical transistors | Leonard Forbes | 2006-09-12 |
| 7105388 | Method of forming at least one interconnection to a source/drain region in silicon-on-insulator integrated circuitry | — | 2006-09-12 |
| 7057223 | Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor | Leonard Forbes | 2006-06-06 |
| 7049196 | Vertical gain cell and array for a dynamic random access memory and method for forming the same | — | 2006-05-23 |
| 7045880 | Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction | Leonard Forbes, Alan R. Reinberg | 2006-05-16 |
| 7023040 | DRAM technology compatible processor/memory chips | Leonard Forbes, Eugene H. Cloud | 2006-04-04 |
| 6964903 | Method of fabricating a transistor on a substrate to operate as a fully depleted structure | Leonard Forbes | 2005-11-15 |
| 6960821 | Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction | Leonard Forbes, Alan R. Reinberg | 2005-11-01 |
| 6946700 | Trench DRAM cell with vertical device and buried word lines | — | 2005-09-20 |
| 6946389 | Method of forming buried conductors | Paul A. Farrar | 2005-09-20 |
| 6936886 | High density SRAM cell with latched vertical transistors | Leonard Forbes | 2005-08-30 |
| 6924194 | DRAM technology compatible processor/memory chips | Leonard Forbes, Eugene H. Cloud | 2005-08-02 |
| 6909635 | Programmable memory cell using charge trapping in a gate oxide | Leonard Forbes, Eugene H. Cloud | 2005-06-21 |
| 6891213 | Base current reversal SRAM memory cell and method | — | 2005-05-10 |
| 6887749 | Multiple oxide thicknesses for merged memory and logic applications | Leonard Forbes | 2005-05-03 |
| 6884687 | SEMICONDUCTOR PROCESSING METHODS OF FORMING INTEGRATED CIRCUITRY, FORMING CONDUCTIVE LINES, FORMING A CONDUCTIVE GRID, FORMING A CONDUCTIVE NETWORK, FORMING AN ELECTRICAL INTERCONNECTION TO A NODE LOCATION, FORMING AN ELECTRICAL INTERCONNECTION WITH A TRANSISTOR SOURCE/DRAIN REGION, AND INTEGRATED CIRCUITRY | — | 2005-04-26 |