Issued Patents All Time
Showing 201–225 of 399 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10276391 | Self-aligned gate caps with an inverted profile | Ruilong Xie, Laertis Economikos | 2019-04-30 |
| 10276689 | Method of forming a vertical field effect transistor (VFET) and a VFET structure | Yi Qi, Jianwei Peng, Hsien-Ching Lo, Ruilong Xie, Xunyuan Zhang | 2019-04-30 |
| 10276560 | Passive device structure and methods of making thereof | Bingwu Liu | 2019-04-30 |
| 10269811 | Selective SAC capping on fin field effect transistor structures and related methods | Min-hwa Chi | 2019-04-23 |
| 10269812 | Forming contacts for VFETs | Ruilong Xie, Lars Liebmann, Daniel Chanemougame, Chanro Park, John H. Zhang +1 more | 2019-04-23 |
| 10269983 | Stacked nanosheet field-effect transistor with air gap spacers | Julien Frougier, Ruilong Xie, Kangguo Cheng, Tenko Yamashita, Chun-Chen Yeh | 2019-04-23 |
| 10263122 | Methods, apparatus, and manufacturing system for self-aligned patterning of contacts in a vertical field effect transistor | Ruilong Xie, Tek Po Rinus Lee, Lars Liebmann | 2019-04-16 |
| 10249538 | Method of forming vertical field effect transistors with different gate lengths and a resulting structure | Yi Qi, Hsien-Ching Lo, Jianwei Peng, Wei Hong, Yanping Shen +5 more | 2019-04-02 |
| 10249616 | Methods of forming a resistor structure between adjacent transistor gates on an integrated circuit product and the resulting devices | Manfred Eller, Haiting Wang, Daniel Jaeger | 2019-04-02 |
| 10243059 | Source/drain parasitic capacitance reduction in FinFET-based semiconductor structure having tucked fins | Srikanth Balaji Samavedan, Manfred Eller, Min-hwa Chi | 2019-03-26 |
| 10236215 | Methods of forming gate contact structures and cross-coupled contact structures for transistor devices | Ruilong Xie, Youngtag Woo, Daniel Chanemougame, Bipul C. Paul, Lars Liebmann +3 more | 2019-03-19 |
| 10236213 | Gate cut structure with liner spacer and related method | Shesh Mani Pandey, Jiehui Shu, Laertis Economikos | 2019-03-19 |
| 10230000 | Vertical-transport transistors with self-aligned contacts | Emilie Bourjot, Daniel Chanemougame, Tek Po Rinus Lee, Ruilong Xie | 2019-03-12 |
| 10217846 | Vertical field effect transistor formation with critical dimension control | Ruilong Xie, Steven Bentley, Min Gyu Sung, Chanro Park, Steven R. Soss +8 more | 2019-02-26 |
| 10217864 | Double gate vertical FinFET semiconductor structure | Josef S. Watts | 2019-02-26 |
| 10211315 | Vertical field-effect transistor having a dielectric spacer between a gate electrode edge and a self-aligned source/drain contact | Haigou Huang | 2019-02-19 |
| 10211206 | Two-port vertical SRAM circuit structure and method for producing the same | Jerome Ciavatti | 2019-02-19 |
| 10204784 | Methods of forming features on integrated circuit products | Jinsheng Gao, Haigou Huang | 2019-02-12 |
| 10204904 | Methods, apparatus and system for vertical finFET device with reduced parasitic capacitance | Rinus Tek Po Lee | 2019-02-12 |
| 10192786 | Process for variable fin pitch and critical dimension | Jinping Liu | 2019-01-29 |
| 10191950 | Identifying influencers using social information | Yi-Min Wang, Phyllis Reuther | 2019-01-29 |
| 10177157 | Transistor structure having multiple n-type and/or p-type elongated regions intersecting under common gate | Min-hwa Chi | 2019-01-08 |
| 10177151 | Single-diffusion break structure for fin-type field effect transistors | Yanzhen Wang, Bingwu Liu | 2019-01-08 |
| 10177037 | Methods of forming a CT pillar between gate structures in a semiconductor | Josef S. Watts | 2019-01-08 |
| 10170377 | Memory cell with recessed source/drain contacts to reduce capacitance | Min-hwa Chi | 2019-01-01 |