Issued Patents All Time
Showing 151–175 of 399 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10522538 | Using source/drain contact cap during gate cut | Haiting Wang, Shesh Mani Pandey, Jiehui Shu, Laertis Economikos, Ruilong Xie +2 more | 2019-12-31 |
| 10522410 | Performing concurrent diffusion break, gate and source/drain contact cut etch processes | Laertis Economikos, Ruilong Xie, Haiting Wang, Hong Yu | 2019-12-31 |
| 10522644 | Different upper and lower spacers for contact | Guowei Xu, Haiting Wang, Scott Beasor | 2019-12-31 |
| 10522639 | Methods, apparatus and system for stringer defect reduction in a trench cut region of a finFET device | Daniel Jaeger, Haigou Huang, Veeraraghavan S. Basker, Christopher Nassar, Jinsheng Gao +1 more | 2019-12-31 |
| 10510749 | Resistor within single diffusion break, and related method | Ruilong Xie, Laertis Economikos, Garo Derderian | 2019-12-17 |
| 10510662 | Vertically oriented metal silicide containing e-fuse device and methods of making same | Chun Yu Wong, Kwan-Yong Lim, Seong Yeol Mun, Jagar Singh | 2019-12-17 |
| 10497692 | SRAM structure with alternate gate pitches | Randy W. Mann | 2019-12-03 |
| 10490455 | Gate contact structures and cross-coupled contact structures for transistor devices | Ruilong Xie, Youngtag Woo, Daniel Chanemougame, Bipul C. Paul, Lars Liebmann +3 more | 2019-11-26 |
| 10483377 | Devices and methods of forming unmerged epitaxy for FinFet device | Bingwu Liu | 2019-11-19 |
| 10475890 | Scaled memory structures or other logic devices with middle of the line cuts | Haiting Wang, Wei Zhao, Hong Yu, Zhenyu Hu, Scott Beasor +3 more | 2019-11-12 |
| 10475899 | Method of forming gate-all-around (GAA) FinFET and GAA FinFET formed thereby | Ruilong Xie, Andreas Knorr, Julien Frougier, Min-hwa Chi | 2019-11-12 |
| 10475693 | Method for forming single diffusion breaks between finFET devices and the resulting devices | Jiehui Shu, Hong Yu, Jinping Liu | 2019-11-12 |
| 10475791 | Transistor fins with different thickness gate dielectric | Garo Derderian, Laertis Economikos, Chun Yu Wong, Jiehui Shu, Shesh Mani Pandey | 2019-11-12 |
| 10468481 | Self-aligned single diffusion break isolation with reduction of strain loss | Haiting Wang, Chun Yu Wong, Kwan-Yong Lim | 2019-11-05 |
| 10461155 | Epitaxial region for embedded source/drain region having uniform thickness | Yoong Hooi Yong, Yanping Shen, Hsien-Ching Lo, Xusheng Wu, Joo Tat Ong +6 more | 2019-10-29 |
| 10461173 | Methods, apparatus, and manufacturing system for forming source and drain regions in a vertical field effect transistor | Ajey Poovannummoottil Jacob, Xuan Anh Tran, Bala Haran, Suryanarayana Kalaga | 2019-10-29 |
| 10446654 | Gate contact structures and self-aligned contact process | Ruilong Xie | 2019-10-15 |
| 10446395 | Self-aligned multiple patterning processes with layered mandrels | Jiehui Shu, Xiaohan Wang, Qiang Fang, Zhiguo Sun, Jinping Liu | 2019-10-15 |
| 10438955 | Devices with contact-to-gate shorting through conductive paths between fins and fabrication methods | Min-hwa Chi | 2019-10-08 |
| 10439026 | Fins with single diffusion break facet improvement using epitaxial insulator | Chun Yu Wong, Xusheng Wu | 2019-10-08 |
| 10431499 | Insulating gate separation structure | Guowei Xu, Haiting Wang, Yue Zhong | 2019-10-01 |
| 10424584 | Semiconductor memory devices having an undercut source/drain region | Manfred Eller | 2019-09-24 |
| 10418272 | Methods, apparatus, and system for a semiconductor device comprising gates with short heights | Jiehui Shu, Garo Derderian, John H. Zhang, Haigou Huang, Jinping Liu | 2019-09-17 |
| 10418285 | Fin field-effect transistor (FinFET) and method of production thereof | Chun Yu Wong, Laertis Economikos | 2019-09-17 |
| 10418365 | Memory array with buried bitlines below vertical field effect transistors of memory cells and a method of forming the memory array | Jerome Ciavatti, Rinus Tek Po Lee | 2019-09-17 |