Issued Patents All Time
Showing 176–200 of 399 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10419437 | Quasi-agentless cloud resource management | Luhui Hu, Ziang Hu | 2019-09-17 |
| 10418272 | Methods, apparatus, and system for a semiconductor device comprising gates with short heights | Jiehui Shu, Garo Derderian, John H. Zhang, Haigou Huang, Jinping Liu | 2019-09-17 |
| 10410933 | Replacement metal gate patterning for nanosheet devices | Ruilong Xie, Chanro Park, Min Gyu Sung, Hoon Kim, Guowei Xu | 2019-09-10 |
| 10410929 | Multiple gate length device with self-aligned top junction | Jianwei Peng, Yi Qi, Hsien-Ching Lo, Jerome Ciavatti, Ruilong Xie | 2019-09-10 |
| 10403734 | Semiconductor device with reduced gate height budget | Haigou Huang | 2019-09-03 |
| 10403548 | Forming single diffusion break and end isolation region after metal gate replacement, and related structure | Hong Yu | 2019-09-03 |
| 10396183 | Parasitic capacitance reducing contact structure in a finFET | Miaomiao Wang, Tenko Yamashita, Chun-Chen Yeh | 2019-08-27 |
| 10396155 | Semiconductor device with recessed source/drain contacts and a gate contact positioned above the active region | Min-hwa Chi | 2019-08-27 |
| 10396000 | Test structure macro for monitoring dimensions of deep trench isolation regions and local trench isolation regions | Tenko Yamashita, Chun-Chen Yeh | 2019-08-27 |
| 10388769 | Parasitic capacitance reducing contact structure in a finFET | Miaomiao Wang, Tenko Yamashita, Chun-Chen Yeh | 2019-08-20 |
| 10388768 | Parasitic capacitance reducing contact structure in a finFET | Miaomiao Wang, Tenko Yamashita, Chun-Chen Yeh | 2019-08-20 |
| 10373875 | Contacts formed with self-aligned cuts | Ruilong Xie, Daniel Jaeger, Chanro Park, Laertis Economikos, Haiting Wang | 2019-08-06 |
| 10374029 | Semiconductor device resistor structure | Josef S. Watts, Shesh Mani Pandey | 2019-08-06 |
| 10373877 | Methods of forming source/drain contact structures on integrated circuit products | Haiting Wang, Hong Yu, Wei Zhao, Yue Zhong, Guowei Xu +3 more | 2019-08-06 |
| 10355101 | Vertical field effect transistor (VFET) having a self-aligned gate/gate extension structure and method | — | 2019-07-16 |
| 10332897 | Method of reducing fin width in FinFet SRAM array to mitigate low voltage strap bit fails | Xiaoqiang Zhang, Ratheesh R. Thankalekshmi, Randy W. Mann | 2019-06-25 |
| 10326002 | Self-aligned gate contact and cross-coupling contact formation | Ruilong Xie, Scott Beasor, Zhenyu Hu | 2019-06-18 |
| 10297452 | Methods of forming a gate contact structure for a transistor | Ruilong Xie, Kangguo Cheng, Tenko Yamashita, Chun-Chen Yeh | 2019-05-21 |
| 10296628 | Sample size estimator | Jiangsheng Yu | 2019-05-21 |
| 10297504 | Methods of forming a gate structure-to-source/drain conductive contact and the resulting devices | Keith H. Tabakman, Ruilong Xie | 2019-05-21 |
| 10290639 | VNW SRAM with trinity cross-couple PD/PU contact and method for producing the same | — | 2019-05-14 |
| 10290712 | LDMOS finFET structures with shallow trench isolation inside the fin | Jerome Ciavatti, Jagar Singh | 2019-05-14 |
| 10290654 | Circuit structures with vertically spaced transistors and fabrication methods | Manfred Eller, Min-hwa Chi | 2019-05-14 |
| 10283621 | Method of forming vertical field effect transistors with self-aligned gates and gate extensions and the resulting structure | Ruilong Xie, Lars Liebmann, Steven Bentley | 2019-05-07 |
| 10283423 | Test structure macro for monitoring dimensions of deep trench isolation regions and local trench isolation regions | Tenko Yamashita, Chun-Chen Yeh | 2019-05-07 |