Issued Patents All Time
Showing 226–250 of 399 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10170353 | Devices and methods for dynamically tunable biasing to backplates and wells | Min-hwa Chi | 2019-01-01 |
| 10170482 | Structure to prevent lateral epitaxial growth in semiconductor devices | Balasubramanian Pranatharthiharan | 2019-01-01 |
| 10170473 | Forming long channel FinFET with short channel vertical FinFET and related integrated circuit | Josef S. Watts, Yi Qi | 2019-01-01 |
| 10163635 | Asymmetric spacer for preventing epitaxial merge between adjacent devices of a semiconductor and related method | Yi Qi, Hsien-Ching Lo, Jerome Ciavatti, Judson R. Holt | 2018-12-25 |
| 10163915 | Vertical SRAM structure | Jerome Ciavatti | 2018-12-25 |
| 10164041 | Method of forming gate-all-around (GAA) FinFET and GAA FinFET formed thereby | Ruilong Xie, Andreas Knorr, Julien Frougier, Min-hwa Chi | 2018-12-25 |
| 10164010 | Finfet diffusion break having protective liner in fin insulator | Wei Hong, Hsien-Ching Lo, Haiting Wang, Yanping Shen, Yi Qi +2 more | 2018-12-25 |
| 10164006 | LDMOS FinFET structures with trench isolation in the drain extension | Jerome Ciavatti, Jagar Singh | 2018-12-25 |
| 10163914 | Method of reducing fin width in FinFET SRAM array to mitigate low voltage strap bit fails | Xiaoqiang Zhang, Ratheesh R. Thankalekshmi, Randy W. Mann | 2018-12-25 |
| 10157927 | Semiconductor memory devices having an undercut source/drain region | Manfred Eller | 2018-12-18 |
| 10153209 | Insulating gate separation structure and methods of making same | Guowei Xu, Haiting Wang, Yue Zhong | 2018-12-11 |
| 10147802 | FINFET circuit structures with vertically spaced transistors and fabrication methods | Manfred Eller, Min-hwa Chi | 2018-12-04 |
| 10147648 | Vertical fin gate structure for RF device | Josef S. Watts | 2018-12-04 |
| 10134739 | Memory array with buried bitlines below vertical field effect transistors of memory cells and a method of forming the memory array | Jerome Ciavatti, Rinus Tek Po Lee | 2018-11-20 |
| 10128187 | Integrated circuit structure having gate contact and method of forming same | Josef S. Watts | 2018-11-13 |
| 10121878 | LDMOS finFET structures with multiple gate structures | Jerome Ciavatti, Jagar Singh | 2018-11-06 |
| 10121893 | Integrated circuit structure without gate contact and method of forming same | Manfred Eller, Min-hwa Chi, Jerome Ciavatti | 2018-11-06 |
| 10121706 | Semiconductor structure including two-dimensional and three-dimensional bonding materials | Rinus Tek Po Lee, Bharat Krishnan, Matthew W. Stoker | 2018-11-06 |
| 10121788 | Fin-type field effect transistors with single-diffusion breaks and method | Haiting Wang, Wei Zhao, Hong Yu, Xusheng Wu, Zhenyu Hu | 2018-11-06 |
| 10115738 | Self-aligned back-plane and well contacts for fully depleted silicon on insulator device | Min-hwa Chi | 2018-10-30 |
| 10115807 | Method, apparatus and system for improved performance using tall fins in finFET devices | Min-hwa Chi, Jinping Liu | 2018-10-30 |
| 10109637 | Cross couple structure for vertical transistors | Randy W. Mann, Bipul C. Paul | 2018-10-23 |
| 10109714 | Buried contact structures for a vertical field-effect transistor | Tek Po Rinus Lee | 2018-10-23 |
| 10103247 | Vertical transistor having buried contact, and contacts using work function metals and silicides | Ruilong Xie, Kangguo Cheng, Tenko Yamashita, Chun-Chen Yeh | 2018-10-16 |
| 10103238 | Nanosheet field-effect transistor with full dielectric isolation | Tek Po Rinus Lee, Haigou Huang, Ruilong Xie, Min Gyu Sung, Chanro Park | 2018-10-16 |