Issued Patents All Time
Showing 251–275 of 399 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10096606 | Methods of forming a gate structure-to-source/drain conductive contact on vertical transistor devices and the resulting transistor devices | — | 2018-10-09 |
| 10096604 | Selective SAC capping on fin field effect transistor structures and related methods | Min-hwa Chi | 2018-10-09 |
| 10090204 | Vertical FINFET structure and methods of forming same | Jae Gon Lee | 2018-10-02 |
| 10090169 | Methods of forming integrated circuit structures including opening filled with insulator in metal gate | Haigou Huang | 2018-10-02 |
| 10083971 | Vertical SRAM structure with cross-coupling contacts penetrating through common gates to bottom S/D metal contacts | Manfred Eller, Kwan-Yong Lim | 2018-09-25 |
| 10079308 | Vertical transistor structure with looped channel | Shesh Mani Pandey, Josef S. Watts | 2018-09-18 |
| 10074732 | Methods of forming short channel and long channel finFET devices so as to adjust threshold voltages | Xinyuan Dou, Hong Yu, Yanzhen Wang | 2018-09-11 |
| 10068921 | Integrated circuits with self aligned contact structures for improved windows and fabrication methods | — | 2018-09-04 |
| 10068902 | Integrated circuit structure incorporating non-planar field effect transistors with different channel region heights and method | Yanping Shen, Hsien-Ching Lo, Yongjun Shi, Randy W. Mann, Yi Qi +4 more | 2018-09-04 |
| 10068766 | Oxidizing and etching of material lines for use in increasing or decreasing critical dimensions of hard mask lines | Min-hwa Chi | 2018-09-04 |
| 10068987 | Vertical field effect transistor (VFET) having a self-aligned gate/gate extension structure and method | — | 2018-09-04 |
| 10056468 | Source/drain parasitic capacitance reduction in FinFET-based semiconductor structure having tucked fins | Srikanth Balaji Samavedan, Manfred Eller, Min-hwa Chi | 2018-08-21 |
| 10050125 | Vertical-transport field-effect transistors with an etched-through source/drain cavity | Yi Qi, Xusheng Wu, Hsien-Ching Lo | 2018-08-14 |
| 10038076 | Parasitic capacitance reducing contact structure in a finFET | Miaomiao Wang, Tenko Yamashita, Chun-Chen Yeh | 2018-07-31 |
| 10038096 | Three-dimensional finFET transistor with portion(s) of the fin channel removed in gate-last flow | Min-hwa Chi | 2018-07-31 |
| 10026740 | DRAM structure with a single diffusion break | Jerome Ciavatti, Josef S. Watts | 2018-07-17 |
| 10014298 | Method of forming field effect transistors with replacement metal gates and contacts and resulting structure | Haigou Huang, Xiaofeng Qiu | 2018-07-03 |
| 10014303 | Devices with contact-to-gate shorting through conductive paths between fins and fabrication methods | Min-hwa Chi | 2018-07-03 |
| 10002940 | Spacer chamfering gate stack scheme | Hyun-Jin Cho, Tenko Yamashita | 2018-06-19 |
| 9991363 | Contact etch stop layer with sacrificial polysilicon layer | Haigou Huang, Jinsheng Gao, Haifeng Sheng, Jinping Liu, Huy Cao | 2018-06-05 |
| 9984932 | Semiconductor fin loop for use with diffusion break | Min-hwa Chi | 2018-05-29 |
| 9960077 | Ultra-scale gate cut pillar with overlay immunity and method for producing the same | Josef S. Watts, Ruilong Xie | 2018-05-01 |
| 9935112 | SRAM cell having dual pass gate transistors and method of making the same | Srikanth B. Samavedam | 2018-04-03 |
| 9935104 | Fin-type field effect transistors with single-diffusion breaks and method | Haiting Wang, Wei Zhao, Hong Yu, Xusheng Wu, Zhenyu Hu | 2018-04-03 |
| 9923046 | Semiconductor device resistor structure | Josef S. Watts, Shesh Mani Pandey | 2018-03-20 |