Issued Patents All Time
Showing 26–50 of 92 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7843015 | Multi-silicide system in integrated circuit technology | Robert J. Chiu, Paul R. Besser, Jeffrey P. Patton, Austin Frenkel, Thorsten Kammler +1 more | 2010-11-30 |
| 7670915 | Contact liner in integrated circuit technology | Errol Todd Ryan, Paul R. Besser, Robert J. Chiu, Mehrdad Mahanpour, Minh Van Ngo | 2010-03-02 |
| 7538383 | Two-bit memory cell having conductive charge storage segments and method for fabricating same | Meng Ding | 2009-05-26 |
| 7498222 | Enhanced etching of a high dielectric constant layer | John Foster, Scott A. Bell, Allison Holbrook, Phillip Jones | 2009-03-03 |
| 7465644 | Isolation region bird's beak suppression | Weidong Qian, Scott A. Bell, Phillip Jones, Allison Holbrook | 2008-12-16 |
| 7456062 | Method of forming a semiconductor device | William G. En, Thorsten Kammler, Eric N. Paton, Paul R. Besser | 2008-11-25 |
| 7446369 | SONOS memory cell having high-K dielectric | Takashi Orimoto, Joong S. Jeon, Hidehiko Shiraiwa, Harpreet Sachar | 2008-11-04 |
| 7381620 | Oxygen elimination for device processing | Boon Yong Ang, Hidehiko Shiraiwa, Harpreet Sachar, Mark Randolph | 2008-06-03 |
| 7265420 | Semiconductor substrate layer configured for inducement of compressive or expansive force | Mario M. Pelella | 2007-09-04 |
| 7250667 | Selectable open circuit and anti-fuse element | Darin A. Chan, Paul L. King | 2007-07-31 |
| 7242102 | Bond pad structure for copper metallization having increased reliability and method for fabricating same | Inkuk Kang, Hiroyuki Kinoshita, Boon Yong Ang, Hajime Wada, Cinti X. Chen | 2007-07-10 |
| 7223640 | Semiconductor component and method of manufacture | Mario M. Pelella, Darin A. Chan | 2007-05-29 |
| 7144818 | Semiconductor substrate and processes therefor | Mario M. Pelella | 2006-12-05 |
| 7132352 | Method of eliminating source/drain junction spiking, and device produced thereby | Paul R. Besser, Jeffrey P. Patton | 2006-11-07 |
| 7122465 | Method for achieving increased control over interconnect line thickness across a wafer and between wafers | Boon Yong Ang, Cinti X. Chen, Inkuk Kang | 2006-10-17 |
| 7064067 | Reduction of lateral silicide growth in integrated circuit technology | Paul L. King, Jeffrey P. Patton, Minh Van Ngo | 2006-06-20 |
| 7023059 | Trenches to reduce lateral silicide growth in integrated circuit technology | Darin A. Chan, Jeffrey P. Patton, Jacques Bertrand | 2006-04-04 |
| 7015076 | Selectable open circuit and anti-fuse element, and fabrication method therefor | Darin A. Chan, Paul L. King | 2006-03-21 |
| 7005357 | Low stress sidewall spacer in integrated circuit technology | Minh Van Ngo, Paul R. Besser, Paul L. King, Errol Todd Ryan, Robert J. Chiu | 2006-02-28 |
| 6969678 | Multi-silicide in integrated circuit technology | Robert J. Chiu, Paul R. Besser, Jeffrey P. Patton, Austin Frenkel, Thorsten Kammler +1 more | 2005-11-29 |
| 6967160 | Method of manufacturing semiconductor device having nickel silicide with reduced interface roughness | Eric N. Paton, Paul R. Besser, Fred N. Hause | 2005-11-22 |
| 6964875 | Array of gate dielectric structures to measure gate dielectric thickness and parasitic capacitance | William G. En, Mark W. Michael, Hai Hong Wang | 2005-11-15 |
| 6873051 | Nickel silicide with reduced interface roughness | Eric N. Paton, Paul R. Besser, Fred N. Hause | 2005-03-29 |
| 6867130 | Enhanced silicidation of polysilicon gate electrodes | Olov Karlsson, William G. En, Mark W. Michael | 2005-03-15 |
| 6841832 | Array of gate dielectric structures to measure gate dielectric thickness and parasitic capacitance | William G. En, Mark W. Michael, Hai Hong Wang | 2005-01-11 |