Issued Patents All Time
Showing 51–75 of 92 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6743666 | Selective thickening of the source-drain and gate areas of field effect transistors | — | 2004-06-01 |
| 6737337 | Method of preventing dopant depletion in surface semiconductor layer of semiconductor-on-insulator (SOI) device | Qi Xiang | 2004-05-18 |
| 6689688 | Method and device using silicide contacts for semiconductor processing | Paul R. Besser, David E. Brown, Eric N. Paton | 2004-02-10 |
| 6670259 | Inert atom implantation method for SOI gettering | — | 2003-12-30 |
| 6642119 | Silicide MOSFET architecture and method of manufacture | Mario M. Pelella, Shankar Sinha | 2003-11-04 |
| 6624476 | Semiconductor-on-insulator (SOI) substrate having selective dopant implant in insulator layer and method of fabricating | Matthew S. Buynoski, Qi Xiang | 2003-09-23 |
| 6537866 | Method of forming narrow insulating spacers for use in reducing minimum component size | Jeffrey A. Shields, Tuan Pham, Jusuke Ogura, Bharath Rangarajan | 2003-03-25 |
| 6518173 | Method for avoiding fluorine contamination of copper interconnects | — | 2003-02-11 |
| 6472317 | Dual damascene arrangement for metal interconnection with low k dielectric constant materials in dielectric layers | Fei Wang, Jerry Cheng, Todd P. Lukanc | 2002-10-29 |
| 6417571 | Single grain copper interconnect with bamboo structure in a trench | Takeshi Nogami | 2002-07-09 |
| 6368949 | Post-spacer etch surface treatment for improved silicide formation | Susan H. Chen | 2002-04-09 |
| 6355575 | Semiconductor device and method of manufacturing without damaging HSQ layer and metal pattern | Fei Wang, Susan H. Chen | 2002-03-12 |
| 6335273 | Surface treatment of low-K SiOF to prevent metal interaction | Richard J. Huang, Guarionex Morales | 2002-01-01 |
| 6333263 | Method of reducing stress corrosion induced voiding of patterned metal layers | Minh Van Ngo, Anne E. Sanderfer, King Wai Kelwin Ko | 2001-12-25 |
| 6312874 | Method for forming a dual damascene trench and underlying borderless via in low dielectric constant materials | Fei Wang, Todd P. Lukanc | 2001-11-06 |
| 6291339 | Bilayer interlayer dielectric having a substantially uniform composite interlayer dielectric constant over pattern features of varying density and method of making the same | Steven C. Avanzino | 2001-09-18 |
| 6258683 | Local interconnection arrangement with reduced junction leakage and method of forming same | Paul R. Besser, Yowjuang Bill Liu | 2001-07-10 |
| 6259115 | Dummy patterning for semiconductor manufacturing processes | Lu You, Kai Yang | 2001-07-10 |
| 6255735 | Dual damascene arrangement for metal interconnection with low k dielectric constant materials in dielectric layers | Fei Wang, Jerry Cheng, Todd P. Lukanc | 2001-07-03 |
| 6251776 | Plasma treatment to reduce stress corrosion induced voiding of patterned metal layers | Minh Van Ngo, Anne E. Sanderfer, King Wai Kelwin Ko | 2001-06-26 |
| 6232663 | Semiconductor device having interlayer insulator and method for fabricating thereof | Toshio Taniguchi, Kenji Nukui, Ibrahim K. Burki, Richard J. Huang, Kazunori Imaoka +1 more | 2001-05-15 |
| 6204136 | Post-spacer etch surface treatment for improved silicide formation | Minh Van Ngo, Paul R. Besser, Angela T. Hui | 2001-03-20 |
| 6200913 | Cure process for manufacture of low dielectric constant interlevel dielectric layers | Lu You, John A. Iacoponi, Richard J. Huang, Robin Cheung | 2001-03-13 |
| 6171919 | MOS Transistor formation process including post-spacer etch surface treatment for improved silicide formation | Paul R. Besser, Minh Van Ngo, Angela T. Hui | 2001-01-09 |
| 6156643 | Method of forming a dual damascene trench and borderless via structure | Fei Wang, Todd P. Lukanc | 2000-12-05 |