SC

Simon S. Chan

AM AMD: 59 patents #99 of 9,279Top 2%
SL Spansion Llc.: 16 patents #40 of 769Top 6%
Cypress Semiconductor: 11 patents #166 of 1,852Top 9%
AV Avantek: 4 patents #4 of 26Top 20%
Globalfoundries: 2 patents #1,397 of 4,424Top 35%
Fujitsu Limited: 2 patents #10,930 of 24,456Top 45%
FL Fujitsu Amd Semiconductor Limited: 1 patents #14 of 40Top 35%
📍 Saratoga, CA: #66 of 2,933 inventorsTop 3%
🗺 California: #2,615 of 386,348 inventorsTop 1%
Overall (All Time): #17,252 of 4,157,543Top 1%
92
Patents All Time

Issued Patents All Time

Showing 76–92 of 92 patents

Patent #TitleCo-InventorsDate
6143672 Method of reducing metal voidings in 0.25 .mu.m AL interconnect Minh Van Ngo, Suzette K. Pangrle, Robert A. Huertas 2000-11-07
6140706 Semiconductor device and method of manufacturing without damaging HSQ layer and metal pattern utilizing multiple dielectric layers Fei Wang, Susan H. Chen 2000-10-31
6124203 Method for forming conformal barrier layers Young-Chang Joo, Dirk Brown 2000-09-26
6093635 High integrity borderless vias with HSQ gap filled patterned conductive layers Khanh Tran, Richard J. Huang, Lu You 2000-07-25
6060380 Antireflective siliconoxynitride hardmask layer used during etching processes in integrated circuit fabrication Ramkumar Subramanian, Bhanwar Singh, Fei Wang 2000-05-09
6043153 Method for reducing electromigration in a copper interconnect Takeshi Nogami 2000-03-28
5994778 Surface treatment of low-k SiOF to prevent metal interaction Richard J. Huang, Guarionex Morales 1999-11-30
5888898 HSQ baking for reduced dielectric constant Minh Van Ngo, Khanh Tran, Terri Jo Kitson, Lu You, Jean Y. Yang 1999-03-30
5861677 Low RC interconnection Lu You, Robin Cheung, Richard J. Huang 1999-01-19
5843836 Tunneling technology for reducing intra-conductive layer capacitance Robin Cheung, Richard J. Huang 1998-12-01
5814560 Metallization sidewall passivation technology for deep sub-half micrometer IC applications Robin Cheung, Subhash Gupta 1998-09-29
5760480 Low RC interconnection Lu You, Robin Cheung, Richard J. Huang 1998-06-02
5670828 Tunneling technology for reducing intra-conductive layer capacitance Robin Cheung, Richard J. Huang 1997-09-23
5288660 Method for forming self-aligned t-shaped transistor electrode Chang-Hwang Hua, Ding-Yuan S. Day 1994-02-22
4978639 Method for the simultaneous formation of via-holes and wraparound plating on semiconductor chips Chang-Hwang Hua, Ding-Yuan S. Day, Adrian Lee 1990-12-18
4842699 Method of selective via-hole and heat sink plating using a metal mask Chang-Hwang Hua, Ding-Yuan S. Day 1989-06-27
4808273 Method of forming completely metallized via holes in semiconductors Chang-Hwang Hua, Ding-Yuan S. Day 1989-02-28