Issued Patents All Time
Showing 26–50 of 71 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6790782 | Process for fabrication of a transistor gate including high-K gate dielectric with in-situ resist trim, gate etch, and high-K dielectric removal | Cyrus E. Tabery, Ming-Ren Lin | 2004-09-14 |
| 6787476 | Etch stop layer for etching FinFET gate over a large topography | Srikanteswara Dakshina-Murthy, Cyrus E. Tabery, Bin Yu | 2004-09-07 |
| 6787854 | Method for forming a fin in a finFET device | Shibly S. Ahmed, Srikanteswara Dakshina-Murthy, Cyrus E. Tabery, Haihong Wang, Bin Yu | 2004-09-07 |
| 6773998 | Modified film stack and patterning strategy for stress compensation and prevention of pattern distortion in amorphous carbon gate patterning | Philip A. Fisher, Marina V. Plat, Christopher F. Lyons, Scott A. Bell, Douglas J. Bonser +2 more | 2004-08-10 |
| 6764949 | Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication | Douglas J. Bonser, Marina V. Plat, Scott A. Bell, Darin A. Chan, Philip A. Fisher +6 more | 2004-07-20 |
| 6764947 | Method for reducing gate line deformation and reducing gate line widths in semiconductor devices | Darin A. Chan, Douglas J. Bonser, Marina V. Plat, Marilyn I. Wright, Lu You +2 more | 2004-07-20 |
| 6764966 | Spacers with a graded dielectric constant for semiconductor devices having a high-K dielectric | William G. En, Arvind Halliyal, Ming-Ren Lin, Minh Van Ngo | 2004-07-20 |
| 6750127 | Method for fabricating a semiconductor device using amorphous carbon having improved etch resistance | Mark S. Chang, Darin A. Chan, Lu You, Scott A. Bell, Srikanteswara Dakshina-Murthy +1 more | 2004-06-15 |
| 6740566 | Ultra-thin resist shallow trench process using high selectivity nitride etch | Christopher F. Lyons, Scott A. Bell, Harry J. Levinson, Khanh B. Nguyen, Fei Wang | 2004-05-25 |
| 6653735 | CVD silicon carbide layer as a BARC and hard mask for gate patterning | Douglas J. Bonser, Pei-Yuan Gao, Lu You | 2003-11-25 |
| 6653231 | Process for reducing the critical dimensions of integrated circuit device features | Uzodinma Okoroanyanwu, Jeffrey A. Shields | 2003-11-25 |
| 6645797 | Method for forming fins in a FinFET device using sacrificial carbon layer | Matthew S. Buynoski, Srikanteswara Dakshina-Murthy, Cyrus E. Tabery, Haihong Wang, Bin Yu | 2003-11-11 |
| 6630288 | Process for forming sub-lithographic photoresist features by modification of the photoresist surface | Jeffrey A. Shields, Uzodinma Okoroanyanwu | 2003-10-07 |
| 6606738 | Analytical model for predicting the operating process window for lithographic patterning techniques based on photoresist trim technology | Scott A. Bell, Marina V. Plat, Amada Wilkison | 2003-08-12 |
| 6599766 | Method for determining an anti reflective coating thickness for patterning a thin film semiconductor layer | Cyrus E. Tabery, Minh Van Ngo | 2003-07-29 |
| 6589709 | Process for preventing deformation of patterned photoresist features | Uzodinma Okoroanyanwu, Jeffrey A. Shields | 2003-07-08 |
| 6579809 | In-situ gate etch process for fabrication of a narrow gate transistor structure with a high-k gate dielectric | Cyrus E. Tabery | 2003-06-17 |
| 6566230 | Shallow trench isolation spacer for weff improvement | Harpreet Sachar, Unsoon Kim, Mark S. Chang, Jayendra D. Bhakta | 2003-05-20 |
| 6563183 | Gate array with multiple dielectric properties and method for forming same | William G. En, Arvind Halliyal, Minh-Ren Lin, Minh Van Ngo, Cyrus E. Tabery | 2003-05-13 |
| 6544885 | Polished hard mask process for conductor layer patterning | Khanh B. Nguyen, Harry J. Levinson, Christopher F. Lyons, Scott A. Bell, Fei Wang | 2003-04-08 |
| 6514871 | Gate etch process with extended CD trim capability | Scott A. Bell | 2003-02-04 |
| 6451647 | Integrated plasma etch of gate and gate dielectric and low power plasma post gate etch removal of high-K residual | Minh Van Ngo | 2002-09-17 |
| 6440640 | Thin resist with transition metal hard mask for via etch application | Christopher F. Lyons, Harry J. Levinson, Khanh B. Nguyen, Fei Wang, Scott A. Bell | 2002-08-27 |
| 6323093 | Process for fabricating a semiconductor device component by oxidizing a silicon hard mask | Qi Xiang, Scott A. Bell | 2001-11-27 |
| 6309926 | Thin resist with nitride hard mask for gate etch application | Scott A. Bell, Christopher F. Lyons, Harry J. Levinson, Khanh B. Nguyen, Fei Wang | 2001-10-30 |