Issued Patents 2020
Showing 25 most recent of 80 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10833266 | Resistive memory crossbar array with ruthenium protection layer | Takashi Ando, Michael Rizzolo, Chih-Chao Yang | 2020-11-10 |
| 10833127 | Three-dimensional and planar memory device co-integration | Takashi Ando, Michael Rizzolo, Chih-Chao Yang | 2020-11-10 |
| 10833010 | Integration of artificial intelligence devices | Hsueh-Chung Chen, Fee Li Lie, Effendi Leobandung | 2020-11-10 |
| 10830841 | Magnetic tunnel junction performance monitoring based on magnetic field coupling | Nicholas Anthony Lanzillo, Benjamin D. Briggs, Michael Rizzolo, Theodorus E. Standaert, James H. Stathis | 2020-11-10 |
| 10831973 | Semiconductor process modeling to enable skip via in place and route flow | Dongbing Shao, Zheng Xu | 2020-11-10 |
| 10833204 | Multiple width nanosheet devices | Kangguo Cheng, Carl Radens, Junli Wang, John H. Zhang | 2020-11-10 |
| 10832945 | Techniques to improve critical dimension width and depth uniformity between features with different layout densities | Nicole Saulnier, Indira Seshadri, Leigh Anne H. Clevenger, Gauri Karve, Fee Li Lie +3 more | 2020-11-10 |
| 10825726 | Metal spacer self aligned multi-patterning integration | Hsueh-Chung Chen, James J. Kelly, Yann Mignot, Cornelius Brown Peethala | 2020-11-03 |
| 10818751 | Nanosheet transistor barrier for electrically isolating the substrate from the source or drain regions | Mona A. Ebrish, Fee Li Lie, Nicolas Loubet, Gauri Karve, Indira Seshadri +1 more | 2020-10-27 |
| 10811599 | Co-fabrication of magnetic device structures with electrical interconnects having reduced resistance through increased conductor grain size | Liying Jiang, Sebastian Naczas, Michael Rizzolo, Chih-Chao Yang | 2020-10-20 |
| 10811310 | Metal spacer self aligned double patterning with airgap integration | Hsueh-Chung Chen, James J. Kelly, Yann Mignot, Cornelius Brown Peethala | 2020-10-20 |
| 10812417 | Auto-incorrect in chatbot human-machine interfaces | Benjamin D. Briggs, Leigh Anne H. Clevenger, Christoper J. Penny, Michael Rizzolo, Aldis Sipolins | 2020-10-20 |
| 10804204 | Multi-chip package structure having chip interconnection bridge which provides power connections between chip and package substrate | Joshua M. Rubin, Charles L. Arvin | 2020-10-13 |
| 10796833 | Magnetic tunnel junction with low series resistance | Nicholas Anthony Lanzillo, Benjamin D. Briggs, Michael Rizzolo, Theodorus E. Standaert, James H. Stathis | 2020-10-06 |
| 10790445 | Protuberant contacts for resistive switching devices | Takashi Ando, Chih-Chao Yang | 2020-09-29 |
| 10785590 | Binaural audio calibration | Benjamin D. Briggs, Leigh Anne H. Clevenger, Christopher J. Penny, Michael Rizzolo, Aldis Sipolins | 2020-09-22 |
| 10784156 | Self-aligned airgaps with conductive lines and vias | Benjamin D. Briggs, Bartlet H. DeProspo, Huai Huang, Christopher J. Penny, Michael Rizzolo | 2020-09-22 |
| 10784197 | Method and structure to construct cylindrical interconnects to reduce resistance | Benjamin D. Briggs, Michael Rizzolo, Christopher J. Penny, Huai Huang, Hosadurga Shobha | 2020-09-22 |
| 10784159 | Semiconductor device and method of forming the semiconductor device | Baozhen Li, Kirk D. Peterson, John E. Sheets, II, Junli Wang, Chih-Chao Yang | 2020-09-22 |
| 10770348 | Location-specific laser annealing to improve interconnect microstructure | Benjamin D. Briggs, Bartlet H. DeProspo, Michael Rizzolo | 2020-09-08 |
| 10770511 | Structures and methods for embedded magnetic random access memory (MRAM) fabrication | Nicholas Anthony Lanzillo, Michael Rizzolo, Theodorus E. Standaert | 2020-09-08 |
| 10763160 | Semiconductor device with selective insulator for improved capacitance | Christopher J. Penny, Benjamin D. Briggs, Michael Rizzolo, Huai Huang, Hosadurga Shobha | 2020-09-01 |
| 10755969 | Multi-patterning techniques for fabricating an array of metal lines with different widths | Albert M. Chu, Kafai Lai | 2020-08-25 |
| 10756260 | Co-fabrication of magnetic device structures with electrical interconnects having reduced resistance through increased conductor grain size | Liying Jiang, Sebastian Naczas, Michael Rizzolo, Chih-Chao Yang | 2020-08-25 |
| 10752039 | Structure of implementing a directed self-assembled security pattern | Benjamin D. Briggs, Bartlet H. DeProspo, Michael Rizzolo | 2020-08-25 |