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Compressive zone to reduce dicing defects |
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Semiconductor device and method of forming the semiconductor device |
Lawrence A. Clevenger, Baozhen Li, John E. Sheets, II, Junli Wang, Chih-Chao Yang |
2020-09-22 |
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Testing mechanism for a proximity fail probability of defects across integrated chips |
Alain G. Rwabukamba, Andrew A. Turner |
2020-09-08 |
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Optimizing error correcting code in three-dimensional stacked memory |
Saravanan Sethuraman, Diyanesh B. Chinnakkonda Vidyapoornachary, Sridhar H. Rangarajan, John Bradley Deforge |
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Shielding structures between optical waveguides |
John J. Ellis-Monaghan, Jeffrey P. Gambino, Mark D. Jaffe, Jed H. Rankin |
2020-07-14 |
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Method of optimizing wire RC for device performance and reliability |
Lawrence A. Clevenger, Baozhen Li, John E. Sheets, II, Terry A. Spooner |
2020-06-30 |
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Step pyramid shaped structure to reduce dicing defects |
Shidong Li, Nicolas Pizzuti, Thomas M. Shaw, Thomas A. Wassick |
2020-04-28 |
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Contacts having a geometry to reduce resistance |
Lawrence A. Clevenger, Baozhen Li, Terry A. Spooner, Junli Wang |
2020-04-28 |
| 10622506 |
Photodiode structures |
John J. Ellis-Monaghan, Jeffrey P. Gambino, Mark D. Jaffe |
2020-04-14 |
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Photodiode structures |
John J. Ellis-Monaghan, Jeffrey P. Gambino, Mark D. Jaffe |
2020-04-07 |
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Managed integrated circuit power supply distribution |
Anthony Gus Aipperspach, Jeffrey Douglas Brown, John E. Sheets, II |
2020-03-03 |
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Three-dimensional stacked memory optimizations for latency and power |
Diyanesh B. Chinnakkonda Vidyapoornachary, John Bradley Deforge, Warren E. Maule, Sridhar H. Rangarajan, Saravanan Sethuraman |
2020-01-14 |
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Three-dimensional stacked memory access optimization |
Diyanesh B. Chinnakkonda Vidyapoornachary, John Bradley Deforge, Warren E. Maule, Sridhar H. Rangarajan, Saravanan Sethuraman |
2020-01-07 |