| 10824504 |
Common high and low random bit error correction logic |
James A. O'Connor, Barry M. Trager, Marc A. Gollub, Brad W. Michael, Patrick J. Meaney |
2020-11-03 |
| 10747442 |
Host controlled data chip address sequencing for a distributed memory buffer system |
Steven R. Carlough, Susan M. Eickhoff, Patrick J. Meaney, Stephen J. Powell, Gary A. Van Huben +1 more |
2020-08-18 |
| 10671497 |
Efficient and selective sparing of bits in memory systems |
Stephen P. Glancy, Kyu-hyoun Kim, Kevin M. Mcilvain |
2020-06-02 |
| 10628248 |
Autonomous dram scrub and error counting |
Diyanesh B. Chinnakkonda Vidyapoornachary, Marc A. Gollub, Tony E. Sawan |
2020-04-21 |
| 10613951 |
Memory mirror invocation upon detecting a correctable error |
Marc A. Gollub, Patrick J. Meaney |
2020-04-07 |
| 10606713 |
Using dual channel memory as single channel memory with command address recovery |
Kyu-hyoun Kim, Kevin M. Mcilvain, Saravanan Sethuraman |
2020-03-31 |
| 10606692 |
Error correction potency improvement via added burst beats in a dram access cycle |
Paul W. Coteus, Kyu-hyoun Kim, Luis A. Lastras-Montano, Patrick J. Meaney, James A. O'Connor +1 more |
2020-03-31 |
| 10592332 |
Auto-disabling DRAM error checking on threshold |
Edgar R. Cordero, Marc A. Gollub, Lucas W. Mulkey, Anuwat Saetow |
2020-03-17 |
| 10546628 |
Using dual channel memory as single channel memory with spares |
Kyu-hyoun Kim, Kevin M. Mcilvain, Saravanan Sethuraman |
2020-01-28 |
| 10534545 |
Three-dimensional stacked memory optimizations for latency and power |
Diyanesh B. Chinnakkonda Vidyapoornachary, John Bradley Deforge, Kirk D. Peterson, Sridhar H. Rangarajan, Saravanan Sethuraman |
2020-01-14 |
| 10528288 |
Three-dimensional stacked memory access optimization |
Diyanesh B. Chinnakkonda Vidyapoornachary, John Bradley Deforge, Kirk D. Peterson, Sridhar H. Rangarajan, Saravanan Sethuraman |
2020-01-07 |
