Issued Patents 2020
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10771068 | Reducing chip latency at a clock boundary by reference clock phase adjustment | Susan M. Eickhoff, Michael W. Harper, Michael B. Spear, Gary A. Van Huben | 2020-09-08 |
| 10747442 | Host controlled data chip address sequencing for a distributed memory buffer system | Susan M. Eickhoff, Warren E. Maule, Patrick J. Meaney, Stephen J. Powell, Gary A. Van Huben +1 more | 2020-08-18 |
| 10740031 | Interface scheduler for a distributed memory system | Jie Zheng, Stephen J. Powell, Susan M. Eickhoff | 2020-08-11 |
| 10725780 | Convert to zoned format from decimal floating point format | Reid T. Copeland, Charles W. Gainey, Jr., Marcel Mitran, Eric M. Schwarz, Timothy J. Slegel | 2020-07-28 |
| 10719324 | Convert to zoned format from decimal floating point format | Reid T. Copeland, Charles W. Gainey, Jr., Marcel Mitran, Eric M. Schwarz, Timothy J. Slegel | 2020-07-21 |
| 10698440 | Reducing latency of memory read operations returning data on a read data path across multiple clock boundaries, to a host implementing a high speed serial interface | Susan M. Eickhoff, Michael B. Spear, Gary A. Van Huben, Stephen D. Wyatt | 2020-06-30 |
| 10671347 | Stochastic rounding floating-point multiply instruction using entropy from a register | Jonathan D. Bradbury, Brian R. Prasky, Eric M. Schwarz | 2020-06-02 |
| 10649738 | Combined residue circuit protecting binary and decimal data | Klaus M. Kroener, Silvia M. Mueller, Andreas Wagner | 2020-05-12 |
| 10642535 | Register access in a distributed memory buffer system | Markus Cebulla, Susan M. Eickhoff, Logan I. Friedman, Patrick J. Meaney, Walter Pietschmann +2 more | 2020-05-05 |
| 10613861 | Programmable linear feedback shift register | Jonathan D. Bradbury, Brian R. Prasky, Eric M. Schwarz | 2020-04-07 |
| 10572223 | Parallel decimal multiplication hardware with a 3x generator | Michael Klein, Michael K. Kroener, Silvia M. Mueller | 2020-02-25 |
| 10541782 | Use of a cyclic redundancy code multiple-input shift register to provide early warning and fail detection | Patrick J. Meaney, Gary A. Van Huben | 2020-01-21 |
| 10534555 | Host synchronized autonomous data chip address sequencer for a distributed buffer memory system | Susan M. Eickhoff, Patrick J. Meaney, Stephen J. Powell, Gary A. Van Huben, Jie Zheng | 2020-01-14 |
| 10530396 | Dynamically adjustable cyclic redundancy code types | Patrick J. Meaney, Gary A. Van Huben | 2020-01-07 |
| 10530523 | Dynamically adjustable cyclic redundancy code rates | Patrick J. Meaney, Gary A. Van Huben | 2020-01-07 |