| 10824504 |
Common high and low random bit error correction logic |
James A. O'Connor, Barry M. Trager, Warren E. Maule, Marc A. Gollub, Brad W. Michael |
2020-11-03 |
| 10824508 |
High efficiency redundant array of independent memory |
Christian Jacobi, Barry M. Trager |
2020-11-03 |
| 10747442 |
Host controlled data chip address sequencing for a distributed memory buffer system |
Steven R. Carlough, Susan M. Eickhoff, Warren E. Maule, Stephen J. Powell, Gary A. Van Huben +1 more |
2020-08-18 |
| 10684968 |
Conditional memory spreading for heterogeneous memory sizes |
David D. Cadigan, Thomas J. Dewkett, Glenn D. Gilda, Craig R. Walters |
2020-06-16 |
| 10673732 |
Dynamic time-domain reflectometry analysis for field replaceable unit isolation in a running system |
Luiz C. Alves, Christopher N. Oelsner, Gary A. Peterson, Christopher W. Steffen |
2020-06-02 |
| 10666540 |
Dynamic time-domain reflectometry analysis for field replaceable unit isolation in a running system |
Luiz C. Alves, Christopher N. Oelsner, Gary A. Peterson, Christopher W. Steffen |
2020-05-26 |
| 10642535 |
Register access in a distributed memory buffer system |
Steven R. Carlough, Markus Cebulla, Susan M. Eickhoff, Logan I. Friedman, Walter Pietschmann +2 more |
2020-05-05 |
| 10613951 |
Memory mirror invocation upon detecting a correctable error |
Marc A. Gollub, Warren E. Maule |
2020-04-07 |
| 10606692 |
Error correction potency improvement via added burst beats in a dram access cycle |
Paul W. Coteus, Kyu-hyoun Kim, Luis A. Lastras-Montano, Warren E. Maule, James A. O'Connor +1 more |
2020-03-31 |
| 10601448 |
Reduced latency error correction decoding |
Glenn D. Gilda, Arthur J. O'Neill, Barry M. Trager |
2020-03-24 |
| 10558519 |
Power-reduced redundant array of independent memory (RAIM) system |
Glenn D. Gilda |
2020-02-11 |
| 10541782 |
Use of a cyclic redundancy code multiple-input shift register to provide early warning and fail detection |
Steven R. Carlough, Gary A. Van Huben |
2020-01-21 |
| 10534555 |
Host synchronized autonomous data chip address sequencer for a distributed buffer memory system |
Steven R. Carlough, Susan M. Eickhoff, Stephen J. Powell, Gary A. Van Huben, Jie Zheng |
2020-01-14 |
| 10530396 |
Dynamically adjustable cyclic redundancy code types |
Steven R. Carlough, Gary A. Van Huben |
2020-01-07 |
| 10530523 |
Dynamically adjustable cyclic redundancy code rates |
Steven R. Carlough, Gary A. Van Huben |
2020-01-07 |
