Issued Patents 2020
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10771068 | Reducing chip latency at a clock boundary by reference clock phase adjustment | Steven R. Carlough, Susan M. Eickhoff, Michael W. Harper, Michael B. Spear | 2020-09-08 |
| 10747442 | Host controlled data chip address sequencing for a distributed memory buffer system | Steven R. Carlough, Susan M. Eickhoff, Warren E. Maule, Patrick J. Meaney, Stephen J. Powell +1 more | 2020-08-18 |
| 10698440 | Reducing latency of memory read operations returning data on a read data path across multiple clock boundaries, to a host implementing a high speed serial interface | Steven R. Carlough, Susan M. Eickhoff, Michael B. Spear, Stephen D. Wyatt | 2020-06-30 |
| 10649511 | Scalable data collection for system management | Irving G. Baysah, John S. Dodson, Karthick Rajamani, Eric E. Retter, Scot H. Rider +3 more | 2020-05-12 |
| 10642535 | Register access in a distributed memory buffer system | Steven R. Carlough, Markus Cebulla, Susan M. Eickhoff, Logan I. Friedman, Patrick J. Meaney +2 more | 2020-05-05 |
| 10541782 | Use of a cyclic redundancy code multiple-input shift register to provide early warning and fail detection | Steven R. Carlough, Patrick J. Meaney | 2020-01-21 |
| 10534555 | Host synchronized autonomous data chip address sequencer for a distributed buffer memory system | Steven R. Carlough, Susan M. Eickhoff, Patrick J. Meaney, Stephen J. Powell, Jie Zheng | 2020-01-14 |
| 10530396 | Dynamically adjustable cyclic redundancy code types | Steven R. Carlough, Patrick J. Meaney | 2020-01-07 |
| 10530523 | Dynamically adjustable cyclic redundancy code rates | Steven R. Carlough, Patrick J. Meaney | 2020-01-07 |