Issued Patents 2020
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10861984 | Integrated cantilever switch | Qing Liu | 2020-12-08 |
| 10833204 | Multiple width nanosheet devices | Kangguo Cheng, Lawrence A. Clevenger, Carl Radens, Junli Wang | 2020-11-10 |
| 10816729 | Hybrid photonic and electronic integrated circuits | — | 2020-10-27 |
| 10804377 | SOI FinFET transistor with strained channel | — | 2020-10-13 |
| 10741698 | Semi-floating gate FET | Qing Liu | 2020-08-11 |
| 10741449 | Stacked transistors with different channel widths | Kangguo Cheng, Lawrence A. Clevenger, Balasubramanian Pranatharthiharan | 2020-08-11 |
| 10734289 | Method for forming strained fin channel devices | Kangguo Cheng, Junli Wang, Lawrence A. Clevenger, Carl Radens | 2020-08-04 |
| 10700214 | Overturned thin film device with self-aligned gate and source/drain (S/D) contacts | Lawrence A. Clevenger, Carl Radens, Yiheng Xu | 2020-06-30 |
| 10700194 | Vertical tunneling FinFET | Qing Liu | 2020-06-30 |
| 10680112 | Gate all around vacuum channel transistor | — | 2020-06-09 |
| 10658459 | Nanosheet transistor with robust source/drain isolation from substrate | Robin Hsin Kuo Chao, Kangguo Cheng, Cheng Chi, Ruilong Xie | 2020-05-19 |
| 10651293 | Methods of simultaneously forming bottom and top spacers on a vertical transistor device | — | 2020-05-12 |
| 10627720 | Overlay mark structures | Lei Sun, Shao Beng Law, Guoxiang Ning, Xunyuan Zhang, Ruilong Xie | 2020-04-21 |
| 10629538 | Modular interconnects for gate-all-around transistors | — | 2020-04-21 |
| 10615177 | Method for manufacturing a transistor having a sharp junction by forming raised source-drain regions before forming gate regions and corresponding transistor produced by said method | — | 2020-04-07 |
| 10615125 | Device and method for alignment of vertically stacked wafers and die | Walter Kleemeier, Paul Ferreira, Ronald K. Sampson | 2020-04-07 |
| 10600638 | Nanosheet transistors with sharp junctions | Kangguo Cheng, Lawrence A. Clevenger, Balasubramanian S. Pranatharthi Haran | 2020-03-24 |
| 10586860 | Method of manufacturing finfet devices using narrow and wide gate cut openings in conjunction with a replacement metal gate process | Jiehui Shu, Laertis Economikos, Xusheng Wu, Haigou Huang, Hui Zhan +4 more | 2020-03-10 |
| 10586741 | Gate height and spacer uniformity | Kangguo Cheng, Lawrence A. Clevenger, Balasubramanian S. Pranatharthi Haran | 2020-03-10 |
| 10573756 | Transistors incorporating metal quantum dots into doped source and drain regions | — | 2020-02-25 |
| 10553497 | Methods and devices for enhancing mobility of charge carriers | Chengyu Niu, Heng Yang | 2020-02-04 |
| 10546789 | Methods of forming metal-gate semiconductor devices with enhanced mobility of charge carriers | Chengyu Niu, Heng Yang | 2020-01-28 |
| 10546743 | Advanced interconnect with air gap | Yann Mignot, Lawrence A. Clevenger, Carl Radens, Richard S. Wise, Yiheng Xu +2 more | 2020-01-28 |