Issued Patents 2020
Showing 1–25 of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10840354 | Approach to bottom dielectric isolation for vertical transport fin field effect transistors | Zhenxing Bi, Thamarai S. Devarajan, Sanjay C. Mehta, Muthumanickam Sankarapandian | 2020-11-17 |
| 10833269 | 3D phase change memory | Wei Wang, Injo Ok, Kevin W. Brew | 2020-11-10 |
| 10833267 | Structure and method to form phase change memory cell with self- align top electrode contact | Injo Ok, Myung-Hee Na, Nicole Saulnier | 2020-11-10 |
| 10832973 | Stress modulation of nFET and pFET fin structures | Huimei Zhou, Kangguo Cheng, Michael P. Belyansky, Oleg Gluschenkov, Richard A. Conti +1 more | 2020-11-10 |
| 10832964 | Replacement contact formation for gate contact over active region with selective metal growth | Ruilong Xie, Chanro Park, Nicolas Loubet | 2020-11-10 |
| 10818773 | Trench silicide contacts with high selectivity process | Andrew M. Greene, Ruilong Xie | 2020-10-27 |
| 10803933 | Self-aligned high density and size adjustable phase change memory | Injo Ok, Myung-Hee Na, Nicole Saulnier | 2020-10-13 |
| 10804159 | Minimize middle-of-line contact line shorts | Injo Ok, Soon-Cheon Seo, Charan V. Surisetty | 2020-10-13 |
| 10797154 | Trench silicide contacts with high selectivity process | Andrew M. Greene, Ruilong Xie | 2020-10-06 |
| 10790284 | Spacer for trench epitaxial structures | Injo Ok, Soon-Cheon Seo, Charan V. V. S. Surisetty | 2020-09-29 |
| 10763326 | Middle-of-line (MOL) capacitance reduction for self-aligned contact in gate stack | Injo Ok, Soon-Cheon Seo, Charan V. V. S. Surisetty | 2020-09-01 |
| 10741449 | Stacked transistors with different channel widths | Kangguo Cheng, Lawrence A. Clevenger, John H. Zhang | 2020-08-11 |
| 10741559 | Spacer for trench epitaxial structures | Injo Ok, Soon-Cheon Seo, Charan V. V. S. Surisetty | 2020-08-11 |
| 10714393 | Middle of the line subtractive self-aligned contacts | Joshua M. Rubin | 2020-07-14 |
| 10707132 | Method to recess cobalt for gate metal application | Georges Jacobi, Vimal Kamineni, Randolph F. Knarr, Muthumanickam Sankarapandian | 2020-07-07 |
| 10699951 | Self-aligned low dielectric constant gate cap and a method of forming the same | Injo Ok, Charan V. V. S. Surisetty | 2020-06-30 |
| 10665512 | Stress modulation of nFET and pFET fin structures | Huimei Zhou, Kangguo Cheng, Michael P. Belyansky, Oleg Gluschenkov, Richard A. Conti +1 more | 2020-05-26 |
| 10643894 | Surface area and Schottky barrier height engineering for contact trench epitaxy | Jody A. Fronheiser, Shogo Mochizuki, Hiroaki Niimi, Mark V. Raymond, Tenko Yamashita | 2020-05-05 |
| 10643893 | Surface area and Schottky barrier height engineering for contact trench epitaxy | Jody A. Fronheiser, Shogo Mochizuki, Hiroaki Niimi, Mark V. Raymond, Tenko Yamashita | 2020-05-05 |
| 10629702 | Approach to bottom dielectric isolation for vertical transport fin field effect transistors | Zhenxing Bi, Thamarai S. Devarajan, Sanjay C. Mehta, Muthumanickam Sankarapandian | 2020-04-21 |
| 10629721 | Contact resistance reduction for advanced technology nodes | Injo Ok, Charan V. Surisetty | 2020-04-21 |
| 10622352 | Fin cut to prevent replacement gate collapse on STI | Andrew M. Greene, Sivananda K. Kanakasabapathy, John R. Sporre | 2020-04-14 |
| 10622458 | Self-aligned contact for vertical field effect transistor | Brent A. Anderson, Steven R. Bentley, Su Chen Fan, Junli Wang, Ruilong Xie | 2020-04-14 |
| 10622259 | Semiconductor devices with sidewall spacers of equal thickness | Kangguo Cheng, Soon-Cheon Seo | 2020-04-14 |
| 10615257 | Patterning method for nanosheet transistors | Injo Ok, Wei Wang, Kevin W. Brew | 2020-04-07 |