Issued Patents 2020
Showing 1–25 of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10879112 | Self-aligned via forming to conductive line and related wiring structure | Edward J. Nowak | 2020-12-29 |
| 10840373 | Integration of input/output device in vertical field-effect transistor technology | Xuefeng Liu, Junli Wang, Terence B. Hook, Gauri Karve | 2020-11-17 |
| 10832975 | Reduced static random access memory (SRAM) device foot print through controlled bottom source/drain placement | Ruqiang Bao, Junli Wang, Kangguo Cheng, Choonghyun Lee, Hemanth Jagannathan | 2020-11-10 |
| 10811507 | Vertical transistors having multiple gate thicknesses for optimizing performance and device density | Fee Li Lie, Stuart A. Sieg, Junli Wang | 2020-10-20 |
| 10811528 | Two step fin etch and reveal for VTFETs and high breakdown LDVTFETs | Mona A. Ebrish, Xuefeng Liu, Huiming Bu, Junli Wang | 2020-10-20 |
| 10811508 | Vertical transistors having multiple gate thicknesses for optimizing performance and device density | Fee Li Lie, Stuart A. Sieg, Junli Wang | 2020-10-20 |
| 10777469 | Self-aligned top spacers for vertical FETs with in situ solid state doping | Ruqiang Bao, Junli Wang, Xin Miao | 2020-09-15 |
| 10777659 | Self-aligned bottom source/drain epitaxial growth in vertical field effect transistors | Choonghyun Lee, Ruqiang Bao, Shogo Mochizuki, Hemanth Jagannathan | 2020-09-15 |
| 10755017 | Cell placement in a circuit with shared inputs and outputs | Laura R. Darden, Albert M. Chu, Alexander J. Suess | 2020-08-25 |
| 10742218 | Vertical transport logic circuit cell with shared pitch | Albert M. Chu | 2020-08-11 |
| 10741544 | Integration of electrostatic discharge protection into vertical fin technology | Huiming Bu, Terence B. Hook, Xuefeng Liu, Junli Wang | 2020-08-11 |
| 10734372 | Vertical transport static random-access memory cells with transistors of active regions arranged in linear rows | Stuart A. Sieg, Junli Wang | 2020-08-04 |
| 10734277 | Top via back end of the line interconnect integration | Chih-Chao Yang, Lawrence A. Clevenger, Benjamin D. Briggs | 2020-08-04 |
| 10727316 | Vertical transistor fabrication and devices | Bruce B. Doris, Seong-Dong Kim, Rajasekhar Venigalla | 2020-07-28 |
| 10720425 | Laterally diffused metal oxide semiconductor device integrated with vertical field effect transistor | Alain Loiseau | 2020-07-21 |
| 10714616 | FINFET having a gate structure in a trench feature in a bent fin | Andres Bryant, Edward J. Nowak | 2020-07-14 |
| 10714396 | Variable gate lengths for vertical transistors | Edward J. Nowak | 2020-07-14 |
| 10672905 | Replacement metal gate process for vertical transport field-effect transistor with self-aligned shared contacts | Ruqiang Bao, Choonghyun Lee, Hemanth Jagannathan | 2020-06-02 |
| 10672670 | Replacement metal gate process for vertical transport field-effect transistors with multiple threshold voltages | Ruqiang Bao, Hemanth Jagannathan, Choonghyun Lee | 2020-06-02 |
| 10629703 | Sloped finFET with methods of forming same | Edward J. Nowak | 2020-04-21 |
| 10629443 | Bottom source/drain silicidation for vertical field-effect transistor (FET) | Huiming Bu, Terence B. Hook, Fee Li Lie, Junli Wang | 2020-04-21 |
| 10622458 | Self-aligned contact for vertical field effect transistor | Steven R. Bentley, Su Chen Fan, Balasubramanian Pranatharthiharan, Junli Wang, Ruilong Xie | 2020-04-14 |
| 10622477 | Fabrication of a vertical field effect transistor device with a modified vertical fin geometry | Edward J. Nowak | 2020-04-14 |
| 10622459 | Vertical transistor fabrication and devices | Bruce B. Doris, Seong-Dong Kim, Rajasekhar Venigalla | 2020-04-14 |
| 10615082 | VFET metal gate patterning for vertical transport field effect transistor | Ruqiang Bao, Kangguo Cheng, Hemanth Jagannathan, Choonghyun Lee, Junli Wang | 2020-04-07 |