Issued Patents 2020
Showing 1–25 of 51 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10840360 | Nanosheet device with close source drain proximity | Veeraraghavan S. Basker, Alexander Reznicek | 2020-11-17 |
| 10840145 | Vertical field-effect transistor devices with non-uniform thickness bottom spacers | Juntao Li, Kangguo Cheng, Choonghyun Lee | 2020-11-17 |
| 10832969 | Single-fin CMOS transistors with embedded and cladded source/drain structures | Xin Miao, Choonghyun Lee, Hemanth Jagannathan | 2020-11-10 |
| 10833192 | Substantially defect free relaxed heterogeneous semiconductor fins on bulk substrates | Veeraraghavan S. Basker, Oleg Gluschenkov, Alexander Reznicek | 2020-11-10 |
| 10818756 | Vertical transport FET having multiple threshold voltages with zero-thickness variation of work function metal | Choonghyun Lee, Kangguo Cheng, Juntao Li | 2020-10-27 |
| 10804270 | Contact formation through low-tempearature epitaxial deposition in semiconductor devices | Oleg Gluschenkov, Hiroaki Niimi, Tenko Yamashita, Chun-Chen Yeh | 2020-10-13 |
| 10784371 | Self aligned top extension formation for vertical transistors | Oleg Gluschenkov, Sanjay C. Mehta, Alexander Reznicek | 2020-09-22 |
| 10777464 | Low thermal budget top source and drain region formation for vertical transistors | Alexander Reznicek, Oleg Gluschenkov | 2020-09-15 |
| 10777659 | Self-aligned bottom source/drain epitaxial growth in vertical field effect transistors | Choonghyun Lee, Ruqiang Bao, Brent A. Anderson, Hemanth Jagannathan | 2020-09-15 |
| 10763343 | Effective junction formation in vertical transistor structures by engineered bottom source/drain epitaxy | Alexander Reznicek | 2020-09-01 |
| 10756170 | VFET devices with improved performance | Kangguo Cheng, Juntao Li, Choonghyun Lee | 2020-08-25 |
| 10756175 | Inner spacer formation and contact resistance reduction in nanosheet transistors | Choonghyun Lee, Kangguo Cheng, Juntao Li | 2020-08-25 |
| 10755985 | Gate metal patterning for tight pitch applications | Alexander Reznicek, Joshua M. Rubin, Junli Wang | 2020-08-25 |
| 10749012 | Formation of self-aligned bottom spacer for vertical transistors | Ruqiang Bao, Hemanth Jagannathan, Choonghyun Lee | 2020-08-18 |
| 10734518 | Substantially defect free relaxed heterogeneous semiconductor fins on bulk substrates | Veeraraghavan S. Basker, Oleg Gluschenkov, Alexander Reznicek | 2020-08-04 |
| 10734490 | Bipolar junction transistor (BJT) with 3D wrap around emitter | Choonghyun Lee, Injo Ok, Soon-Cheon Seo | 2020-08-04 |
| 10734281 | Method and structure to fabricate a nanoporous membrane | Zhenxing Bi, Kangguo Cheng, Hao Tang | 2020-08-04 |
| 10714399 | Gate-last process for vertical transport field-effect transistor | Choonghyun Lee, Hemanth Jagannathan | 2020-07-14 |
| 10707329 | Vertical fin field effect transistor device with reduced gate variation and reduced capacitance | Juntao Li, Kangguo Cheng, Choonghyun Lee | 2020-07-07 |
| 10700062 | Vertical transport field-effect transistors with uniform threshold voltage | Choonghyun Lee, Kangguo Cheng, Juntao Li | 2020-06-30 |
| 10692868 | Contact formation through low-temperature epitaxial deposition in semiconductor devices | Oleg Gluschenkov, Hiroaki Niimi, Tenko Yamashita, Chun-Chen Yeh | 2020-06-23 |
| 10686057 | Vertical transport FET devices having a sacrificial doped layer | Choonghyun Lee, Kangguo Cheng, Juntao Li | 2020-06-16 |
| 10679901 | Differing device characteristics on a single wafer by selective etch | Huimei Zhou, Gen Tsutsui, Ruqiang Bao | 2020-06-09 |
| 10680102 | Reduction of top source/drain external resistance and parasitic capacitance in vertical transistors | Choonghyun Lee, Kangguo Cheng, Juntao Li | 2020-06-09 |
| 10665714 | Vertical transistors with various gate lengths | Juntao Li, Kangguo Cheng, Choonghyun Lee | 2020-05-26 |