Issued Patents 2020
Showing 26–50 of 51 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10665714 | Vertical transistors with various gate lengths | Juntao Li, Kangguo Cheng, Choonghyun Lee | 2020-05-26 |
| 10651089 | Low thermal budget top source and drain region formation for vertical transistors | Alexander Reznicek, Oleg Gluschenkov | 2020-05-12 |
| 10651308 | Self aligned top extension formation for vertical transistors | Oleg Gluschenkov, Sanjay C. Mehta, Alexander Reznicek | 2020-05-12 |
| 10651295 | Forming a fin using double trench epitaxy | Veeraraghavan S. Basker, Pouya Hashemi, Alexander Reznicek | 2020-05-12 |
| 10644138 | Fin field-effect transistors with enhanced strain and reduced parasitic capacitance | Kangguo Cheng, Juntao Li, Choonghyun Lee | 2020-05-05 |
| 10643894 | Surface area and Schottky barrier height engineering for contact trench epitaxy | Jody A. Fronheiser, Hiroaki Niimi, Balasubramanian Pranatharthiharan, Mark V. Raymond, Tenko Yamashita | 2020-05-05 |
| 10643893 | Surface area and Schottky barrier height engineering for contact trench epitaxy | Jody A. Fronheiser, Hiroaki Niimi, Balasubramanian Pranatharthiharan, Mark V. Raymond, Tenko Yamashita | 2020-05-05 |
| 10628404 | Vertical transistor and method of forming the vertical transistor | Fee Li Lie, Junli Wang | 2020-04-21 |
| 10622379 | Structure and method to form defect free high-mobility semiconductor fins on insulator | Veeraraghavan S. Basker, Oleg Gluschenkov, Alexander Reznicek | 2020-04-14 |
| 10622489 | Vertical tunnel FET with self-aligned heterojunction | Chun Wing Yeung, Choonghyun Lee, Ruqiang Bao | 2020-04-14 |
| 10615083 | Formation of common interfacial layer on Si/SiGe dual channel complementary metal oxide semiconductor device | Ruqiang Bao, Hemanth Jagannathan, Choonghyun Lee | 2020-04-07 |
| 10600695 | Channel strain formation in vertical transport FETS with dummy stressor materials | Choonghyun Lee, Kangguo Cheng, Juntao Li | 2020-03-24 |
| 10600885 | Vertical fin field effect transistor devices with self-aligned source and drain junctions | Kangguo Cheng, Juntao Li, Choonghyun Lee | 2020-03-24 |
| 10600694 | Gate metal patterning for tight pitch applications | Alexander Reznicek, Joshua M. Rubin, Junli Wang | 2020-03-24 |
| 10593797 | Vertical transport field effect transistor structure with self-aligned top junction through early top source/drain epitaxy | Brent A. Anderson, Hemanth Jagannathan, Junli Wang | 2020-03-17 |
| 10586769 | Contact formation in semiconductor devices | Oleg Gluschenkov, Jiseok Kim, Zuoguang Liu, Hiroaki Niimi | 2020-03-10 |
| 10573567 | Sacrificial cap for forming semiconductor contact | Praneet Adusumilli, Zuoguang Liu, Jie Yang, Chun Wing Yeung | 2020-02-25 |
| 10573746 | VTFET devices utilizing low temperature selective epitaxy | Hemanth Jagannathan | 2020-02-25 |
| 10573727 | Vertical transistor device | Brent A. Anderson, Huiming Bu, Fee Li Lie, Junli Wang | 2020-02-25 |
| 10573521 | Gate metal patterning to avoid gate stack attack due to excessive wet etching | Junli Wang, Alexander Reznicek, Joshua M. Rubin | 2020-02-25 |
| 10559566 | Reduction of multi-threshold voltage patterning damage in nanosheet device structure | Choonghyun Lee, Kangguo Cheng, Juntao Li | 2020-02-11 |
| 10553716 | Formation of a bottom source-drain for vertical field-effect transistors | Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Junli Wang | 2020-02-04 |
| 10541331 | Fabrication of a vertical fin field effect transistor with an asymmetric gate structure | Junli Wang | 2020-01-21 |
| 10535773 | FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formation | Dechao Guo, Hemanth Jagannathan, Gen Tsutsui, Chun-Chen Yeh | 2020-01-14 |
| 10529828 | Method of forming vertical transistor having dual bottom spacers | Oleg Gluschenkov, Sanjay C. Mehta, Alexander Reznicek | 2020-01-07 |